The Improvement of FN Degradation in 3-Dimension TR

Wednesday, May 14, 2014
Grand Foyer, Lobby Level (Hilton Orlando Bonnet Creek)
S. Y. Ha, S. G. Park (Samsung Electronics Co., Ltd, Sungkyunkwan University), S. D. Kim, H. C. Kim, K. P. Lee (Samsung Electronics Co., Ltd), and I. S. Jung (Sungkyunkwan University)
As Transistor length shrink, many unexpected short channel effects occur under 20nm size. Among these short channel effects, this paper explains about reliability problem of FN degradation and its improvement in 3-Dimension Transistor. The graph of Fig.1 demonstrates that there was threshold voltage(Vth) shift after reliability test(High voltage, High temperature, Long time condition). Of course, the original black curve must be maintained its value despite of reliability stress. This phenomenon caused serious reliability problem in the device.

Above all the easiest method to solve this problem was that we increased the thickness of the oxide. However this method had serious demerit that we must endured the current decrease [1]. Therefore the following two methods were considered for solving this problem.

The first method was that we changed the profile of FIN to reduce the leakage current. The electric fields were crowded at the sharp point and degradation could occur well in Fig.2 (a) profile-1. Therefore we made the sharp point be rounded like Fig.2 (b) profile-2 by changing FIN shape. This was good solution to protect charge converging on cusp and to reduce FN degradation. In the graph of Fig.4 we could confirm that profile-2 was better than profile-1. However this method must be applied carefully in device because it generated side effects that were caused by decreased margin of Gate to Active isolation.

The second method was that we reduced fixed charges generation by adjusting the grain size of metal gate. The grain size of metal gate was more lager after all integration than just deposition status. This grain growth acted as (+) charge formation factor in the condition of reliability stress. In other words, at the interface of Si and metal gate the following reaction happened lively (TiN + SiO2 -> TiON + SiO+ ). Therefore we must reduce the grain growth to improve the FN degradation. We knew that the grain size was changed by temperature of TiN deposition through many experiments [2]. In Fig.3 (a), the grain size grew approximately 0.8nm per 30 degrees of TiN deposition temperature. As the TiN deposition temperature increased, gap of grain growth became smaller than low temperature status. It noted that the grain size after all integration is almost same as the grain size of just deposition status like Fig.3 (b) which is real grain TEM image in condition of 660°C.

In conclusion, to confirm enhancement we verified the result of FIN profile optimization and TiN deposition temperature experiment by measuring Vth shift. In Fig.4, Vth shift and residual stress became smaller and smaller as we applied improvement condition.


[1] Fundamentals of Modern VLSI Devices, by Yuan Taur and Tak H.Ning

[2] Hsyi-En Cheng, Wen-Jen Lee, C.-M. Hsu, Thin Solid Films Volume 485, Issues 1–2, 1 August 2005, Pages 59–65