Novel Poly Gate Shaping by Wet Etch Process in 2xnm NAND Flash Device and Beyond

As Moore’s law, critical dimension (CD) become smaller and smaller, and CD control become the task of process developing and wafer fabrication. Gate shrinkage by wet process is one choice of non-lithography techniques to achieve smaller CD requirement.

The common wet chemicals used in poly silicon etch, such as NH₄OH, KOH, TMAH, HF/HNO₃mixture, SC1, are usually limited in metal non-adapted process or intrinsically high etch rate of low-thermal-budget (small crystal grain size) /high- phosphorus-dosage poly silicon. Moreover, the unique etching behaviors of former mentioned chemicals are lattice dependency and higher etching rate along poly silicon grain boundary. This paper successfully demonstrated reversed trend of higher thermal budget and non-doped poly silicon with higher wet etching rate, and smooth etching surface by adding ionic surfactant. The unique properties can be used in metal adapted flash gate shrinkage and get adjustable shrinkage amount between control gate and floating gate poly silicon with different thermal budget and dopant dosages.

           Figure 1 shows three kinds of poly silicon, Non-doped poly silicon with high thermal budget (ND-HT), high phosphorous dosage doped with high thermal budget (HD-HT) and high phosphorous dosage doped with low thermal budget (HD-LT), etch rate are collected by three levels ionic surfactant concentrations in TMAH chemical, TMAH with low ionic surfactant concentration (L-TMAH), TMAH with medium ionic surfactant concentration (M-TMAH) and TMAH with high ionic surfactant concentration (H-TMAH). With increased ionic surfactant amount, high-phosphorous-doped poly silicon etching rate is obviously decreased. In H-TMAH split, HD-HT and HD-LT etching rate become similar. From selectivity curve, the selectivity of ND-HT/HD-HT (dosage difference) and ND-HT/HD-LT (dosage and thermal budget difference) increase with ionic surfactant amount increased, but selectivity of HD-HT/HD-LT (thermal budget difference) decrease. It means thermal budget effect is suppressed by higher ionic surfactant amount, and etch rate of high phosphorous doped poly silicon becomes lower than non-doped poly silicon.

           In 2xnm NAND Flash process and beyond, smaller gate pitch and higher aspect ratio are the process tasks to dry and wet etching. Taper gate etching profile is inevitable, and easily result in gate to gate leak or short issue. Floating gate poly silicon (FG) is usually with lower phosphorous doped and with higher thermal budget, and control gate poly silicon (CG) is usually with higher phosphorous doped and with lower thermal budget. Based on the unique property of higher ionic surfactant concentration in TMAH, gate shaping application is proposed. Poly gate profile can be modified, such as floating gate poly silicon footing issue, and get smaller gate critical dimension, shows as Figure 2.

           Figure 3-a and 3-b indicate that two TMAH splits, with high and low concentration of ionic surfactants, are adopted to gate structure in 2xnm NAND Flash process and TEM images show, after H-TMAH treatment, more FG bottom CD shrink and sidewall profile smoother than L-TMAH. Table 1 shows FG/CG etching selectivity of L-TMAH is around 0.8 and H-TMAH is around 3.22.

           By adjusting ionic surfactant ratio in TMAH, poly silicon, with different phosphorous doped dosage and thermal budget, shrinkage amount can be precisely adjusted.