Electronic Materials and Processing

Monday, May 12, 2014

Monday | Tuesday | Wednesday | top

08:50-09:30

P2: Silicon Compatible Materials, Processes and Technologies for Advanced Integrated Circuits and Emerging Applications 4


Welcome and Plenary Session
Flagler, Ground Level
Chair(s): F. Roozeboom and P. J. Timans

10:00-12:20

P2: Silicon Compatible Materials, Processes and Technologies for Advanced Integrated Circuits and Emerging Applications 4


Advanced Processes for FEOL/BEOL Applications
Flagler, Ground Level
Chair(s): Kuniyuki Kakushima and Vijay Narayanan

14:00-16:30

P2: Silicon Compatible Materials, Processes and Technologies for Advanced Integrated Circuits and Emerging Applications 4


New Functional Areas
Flagler, Ground Level
Chair(s): Kuniyuki Kakushima and Vijay Narayanan

Tuesday, May 13, 2014

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08:20-09:30

P1: Chemical Mechanical Polishing 13


CMP of Metals
Bonnet Creek Ballroom VII, Lobby Level
Chair(s): Yaw S. Obeng

09:00-12:00

P2: Silicon Compatible Materials, Processes and Technologies for Advanced Integrated Circuits and Emerging Applications 4


Emerging Device Architectures-FINFETs/ETSOI/Nanowires
Flagler, Ground Level
Chair(s): Vijay Narayanan and Kuniyuki Kakushima

10:00-11:40

P1: Chemical Mechanical Polishing 13


CMP of Dielectrics
Bonnet Creek Ballroom VII, Lobby Level
Chair(s): Iqbal Ali

14:00-15:20

P1: Chemical Mechanical Polishing 13


CMP Integration and Control
Bonnet Creek Ballroom VII, Lobby Level
Chair(s): Gautam Banerjee

14:00-17:40

P2: Silicon Compatible Materials, Processes and Technologies for Advanced Integrated Circuits and Emerging Applications 4


High Mobility Channels
Flagler, Ground Level
Chair(s): Evgeni Gousev and P. J. Timans

15:40-16:50

P1: Chemical Mechanical Polishing 13


Current Topics in CMP
Bonnet Creek Ballroom VII, Lobby Level
Chair(s): G. Bahar Basim

18:00-20:00

P1: Chemical Mechanical Polishing 13


P1 CMP Poster Session
Grand Foyer, Lobby Level

P2: Silicon Compatible Materials, Processes and Technologies for Advanced Integrated Circuits and Emerging Applications 4


P2 Poster Session
Grand Foyer, Lobby Level

Wednesday, May 14, 2014

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08:20-11:55

P2: Silicon Compatible Materials, Processes and Technologies for Advanced Integrated Circuits and Emerging Applications 4


3D Integration and Microsystems
Flagler, Ground Level
Chair(s): Paul A Kohl and O. M. Leonte