Emerging Device Architectures-FINFETs/ETSOI/Nanowires

Tuesday, May 13, 2014: 09:00-12:00
Flagler, Ground Level (Hilton Orlando Bonnet Creek)
Chairs:
Vijay Narayanan and Kuniyuki Kakushima
09:00
1449
(Invited) Material Engineering for 7nm FinFETs
V. Moroz, J. Huang, M. Choi, and L. Smith (Synopsys, Inc.)
09:40
Break
10:00
1450
(Invited) Challenges in Contact Technologies for Planar/Non-Planar Si Technologies
P. Adusumilli, E. Alptekin, and N. Breil (IBM Semiconductor Research and Development Center)
10:40
1451
Back Gate Bias Stressing on Extremely Thin SOI (ETSOI) MOSFETs with Gate Last Process Integration
Z. Tang, B. Tang, L. Zhao, G. Wang, J. Xu, Y. Xu, H. Wang, D. Wang, J. Li, J. Yan, and C. Zhao (Institute of Microelectronics of Chinese Academy of Sciences)
 
1452
(Invited) Effect of SOI Substrate on CMOS Devices Reliability (Cancelled)
11:40
1453
Growth of the Manganese Silicide/Silicon Nanowire Heterostructures and Their Physical Properties
Y. S. Hsieh, C. W. Huang, C. H. Chiu (Department of Material science and engineering, National Chiao Tung University), K. C. Lu (Department of Materials Science and Engineering, National Cheng Kung University), and W. W. Wu (Department of Material science and engineering, National Chiao Tung University)
See more of: P2: Silicon Compatible Materials, Processes and Technologies for Advanced Integrated Circuits and Emerging Applications 4
See more of: Electronic Materials and Processing
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