Back Gate Bias Stressing on Extremely Thin SOI (ETSOI) MOSFETs with Gate Last Process Integration

Full depleted extremely thin SOI (ETSOI) is viewed as a promising device due to its excellent immunity to short channel effect (SCE) especially with applying of back gate bias stressing. In this paper, SOI transistors fabricated with gate last process scheme with thin channel layers of 4 to 11nm are provided with superior device performance. For a given gate length less than 30nm, DIBL and Swing are achieved with 40mV/V and 78mV/Dec respectively with stressing of back gate bias. Threshold voltage can be tuned within range of 0.8 volts (V_dd=-0.05v). It is large enough for adjusting device performance. Also, from our results, it is shown that device with thicker channel layer of 11nm are more sensitive to back gate bias comparing with that with thinner channel layer of 4nm. It demonstrates electrical characteristic of ETSOI with thicker channel layer is propitious to be adjusted, while that is more convergent with thinner channel layer.

Figure.1. shows the detail integration flow of ETSOI with HKMG and TEM of cross section of gate structure. In Fig. 2, Id-Vg curves for different channel thickness are plotted. It can be seen that shift of voltage with thicker channel layer of 11nm is larger than that with thinner channel layer of 4nm. Fig. 3 displays Vt difference under back gate bias stressing for different channel thickness.

In conclusion, we have successfully fabricated extremely thin SOI (ETSOI) devices with both HK and MG last integration scheme. Excellent device performances are achieved and back gate bias stressing on device characteristic is analyzed. With thicker channel layers, devices are more sensitive to back gate bias, while with thinner channel layers; devices are more convergent for electrical characteristic.

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