(Invited) Effect of SOI Substrate on CMOS Devices Reliability
Performance of FDSOI technology:
FDSOI (Fully Depleted SOI, Figure 1) technology process has been evidenced as very attractive for low power application due to the very good control of short channel effects and very good isolation of neighboring devices. Besides, the use of undopped channel improves mobility in the channel mobility as well as device matching. Finally, the proposed architecture allows a wide range of operation back bias and the possibility to adapt the device performance or power consumption dynamically with very limited reliability penalty regardless the performance gain.
Burried oxide reliability
Buried Oxide reliability was characterized by means of linear voltage ramp stress constant voltage stress. Breakdown voltage is found above 30V, and time to breakdown having several decades of margin at operating voltage (figure 2). Besides, transistor parameters drift under back bias stress occurs above 20V and also exhibit large lifetime margins (Figure 3).
MOS device reliability
A direct comparison of 28nm bulk vs 28nm SOI technology shows that gate dielectrics related failure modes (time dependent breakdown and transistor parameter drift under vertical electrical field and / or hot carrier injection) are un-affected by the presence of buried oxide (Figure 4), since the vertical electrical field and gate stack composition are the same. At the same time, we also evidenced that additional back bias does not influence on tddb and BTI (Figure5). This finding is consistent with screening of applied back bias by the inversion layer. Additionally, we analyzed electrical defect signature to track the defect generation on the channel back-side[3,4]. It was found that in extreme back bias configuration only (>4-6V), defects can be generated at bottom interface. We also reported a full characterization of Tsi (figure 6) and back bias (figure 7) effect on HCI defect generation confirming the primary effect of carrier energy over carrier density giving a comprehensive framework to the general behavior of 28FDSOI performance-reliability trade-off (figure 8).
28nm FDSOI devices were submitted to electrical reliability. Intrinsic buried oxide reliability as well as effect of Tsi and Vb on transistors failure mode were quantified to be implemented in circuit simulators.
 Planes N., VLSI 2012
 Arnaud F., IEDM 2012
 Brunet L., IEEE SOI conference 2009