P2 Silicon Compatible Materials, Processes and Technologies for Advanced Integrated Circuits and Emerging Applications 4

Lead Organizer: F. Roozeboom (Eindhoven University of Technology)

Co-organizers: E. P. Gusev (Qualcomm Technologies, Inc.) , Hiroshi Iwai (Tokyo Institute of Technology) , Kuniyuki Kakushima (Tokyo Institute of Technology) , Vijay Narayanan (IBM T.J. Watson Research Center) , P. J. Timans (Thermal Process Solutions Ltd.) , Paul A Kohl (Georgia Institute of Technology) and O. M. Leonte (Berkeley Polymer Technologies, Inc.)

Monday, May 12, 2014

08:50-09:30


Welcome and Plenary Session
Flagler, Ground Level
Chair(s): F. Roozeboom and P. J. Timans

10:00-12:20


Advanced Processes for FEOL/BEOL Applications
Flagler, Ground Level
Chair(s): Kuniyuki Kakushima and Vijay Narayanan

14:00-16:30


New Functional Areas
Flagler, Ground Level
Chair(s): Kuniyuki Kakushima and Vijay Narayanan

Tuesday, May 13, 2014

09:00-12:00


Emerging Device Architectures-FINFETs/ETSOI/Nanowires
Flagler, Ground Level
Chair(s): Vijay Narayanan and Kuniyuki Kakushima

14:00-17:40


High Mobility Channels
Flagler, Ground Level
Chair(s): Evgeni Gousev and P. J. Timans

18:00-20:00


P2 Poster Session
Grand Foyer, Lobby Level

Wednesday, May 14, 2014

08:20-11:55


3D Integration and Microsystems
Flagler, Ground Level
Chair(s): Paul A Kohl and O. M. Leonte