(Invited) Challenges in Contact Technologies for Planar/Non-Planar Si Technologies

The transition from 2D planar devices to 3D devices that is underway in the semiconductor industry has significant implications for parasitic resistance & capacitance of CMOS devices. This talk will focus on challenges in contact technologies as we make this transition.

 Increases in the width of the channel per foot print and the simultaneous scaling of gate pitch have accelerated the shrink in effective contact area per channel width and has elevated the importance of contact length for formation of low resistance contacts.

 Additionally, scaling of gate pitch is leading to new concerns about device yield and defectivity - such as shorts between interconnect contacts due to increase in contact critical dimensions post patterning. This has put renewed focus on anisotropic cleans and other surface preparation techniques. A nominal increase in contact critical dimensions while beneficial for parasitic resistance has a capacitance penalty and this trade off needs to be carefully managed.

 Furthermore, an increase in material and process integration complexity adds to the challenge of engineering the specific contact resistivity of the contact metal/source-drain interface. For example, the impact of down stream thermal processing on dopant activation in the source-drain regions needs particular attention.

 Finally, the contribution from interconnect metallization to the overall parasitic resistance is on the rise and needs to be mitigated.