(Invited) Material Engineering for 7nm FinFETs

Recently, several enabling technologies have become available for integrating non-Si channels on Si wafers, including HKMG with acceptable trap densities, aspect ratio trapping, and low temperature epitaxy with in-situ doping. This considerably broadens the list of potential candidate materials for the 7nm technology node in search of exceeding performance of Si FinFETs.

The search for the alternative channel materials is often motivated by high levels of carrier mobility in bulk material. Some promising demonstrations have been done with long channel transistors. However, the bulk carrier mobility is not relevant for performance of the short channel transistors. The target channel length for the 7nm node is about 15 nm, with most of the carriers exhibiting ballistic transport without experiencing scattering events when moving from source to drain. The ballistic transport favors materials with lighter effective carrier mass in terms of the driving current strength. On the flip side, such materials exhibit higher off-state leakage currents via band-to-band tunneling and direct source-to-drain tunneling mechanisms. So, instead of being guided by the bulk carrier mobility numbers, a more appropriate approach is to evaluate the trade-off between the on-state and the off-state current levels for the particular combination of material properties and transistor design rules.

In this work, we assume that the process-related issues such as defects can be resolved over time and focus on performance of defect-free materials, with performance determined by fundamental material properties. This way, we can get the upper bound on performance for each candidate material and see if it is worth pursuing in terms of struggling through laborious process integration.

Besides the on-state and off-state currents, several other key metrics are included into the trade-off analysis, such as self-heating and the ability to withstand and dissipate the heat, and parasitic R and C of the MOL.

The comparative analysis of several candidate channel materials is performed considering four technology flavors: HP, SP, and LP logic, and the I/O transistors. The appropriate modeling methodologies are introduced to cover these materials and the target design rules.