1390
Charge Trapping Characterization of LaLuO3/p-Si Interfaces at Cryogenic Temperatures

Wednesday, May 14, 2014
Grand Foyer, Lobby Level (Hilton Orlando Bonnet Creek)
I. P. Tyagulskyy, S. I. Tiagulskyi, A. N. Nazarov, V. S. Lysenko (Lashkaryov Institute of Semiconductor Physics, NASU), P. K. Hurley, K. Cherkaoui, and S. Monaghan (University College Cork)
Ternary rare-earth oxide LaLuO3 shows clear experimental evidence of being one of the most perspective gate dielectrics for application in upcoming MOSFET technology [1]. On the one hand, these oxides are thermally stable in the amorphous phase and possess high permittivity, and, on the other hand, complex composition of the oxide leads to more heterogeneity and defectiveness of the dielectric – semiconductor transition layer (TL). Therefore the study of electronic processes in the transition layers LaLuO3/Si is one of the major challenges associated with further implementation of the LaLuO3in CMOS technology.

       In this article we present an experimental investigation of charge trapping and emission from shallow traps in the TL of the LaLuO3 /p-Si structures in the temperature range 6– 40 K, which allows us to estimate quality of the gate dielectric TL. The experimental approach adopted in this work is based on the techniques of thermally stimulated charge release (TSCR), isothermal transient emission currents (ITC), dynamic I(V) characteristics and extends on our previous reports of applying the technique to study charge trapping in TL of LaSiOx /Si, GdSiOx /Si [2], HfO2/Si [3] and SiO2/Si structures [4].

        The dielectric layers in the Pt/LaLuO3/p-Si(100) MOS structures were deposited by molecular beam deposition. Evaporation of La and Lu in O2 was performed at a substrate temperature of 450°C. Nominal physical thicknesses of LaLuO3 were 6.5 nm and 20 nm. The Pt gates (area - 1×10-4 cm2 ) were prepared by e-gun evaporation through a shadow mask. The MOS stacks were annealed in forming gas at 400°C for 10 minutes (10% H2).

        The TSCR spectra for the Pt/LaLuO3 /p-Si structure for different charging temperatures are presented in Fig. 1. Regimes of trap’s charging are depicted on the field of Fig.1. Some peculiarities of thermally stimulated currents need to be point out. At first, the TSC peak shifts towards lower temperatures, when charging temperature decreases. At second, amplitude of the TSC peak grows steadily when accumulation charging voltage (Vch) increases (not shown here).
     The activation energy of the TSC process was found using the initial rise method. Activation energies for hole traps have been as much as 24.3–27.9 meV, 30.3–30.6 meV and 36–39 meV (LaLuO3 thickness - 6.5nm) and 12.3-12.4 meV, 21.1-22meV, 23.4-24.4 meV (LaLuO3 thickness - 20nm). The total concentration of hole shallow traps is as large as 6.2×1010cm-2  for LaLuO3 thickness 6.5nm and 4.1×1010cm-2  for  thickness 20nm.
     The strong current relaxation has been found to occur after Vthswitching-off (see Fig.2). Approximating relaxation time by exponential decay function from 1/τ~ f(1/kT) dependence activation energy of relaxation processes (8.8 meV) have been determined.

          Formation of TSCR spectra in the LaLuO3/p-Si structures is supposed to result from the recharging of traps, localized in the transition layer. The process of recharging of the traps may be due to the tunnel –
activation mechanism assisted by phonons localized on the defects in transition layer.

    This work was partially supported by NAS of Ukraine (the project No. 53-32-10). The authors from Tyndall National Institute acknowledge the financial support of Science Foundation Ireland through the project 09/IN.1/I2633.

1. E. Durğun Őzben, J.M.J. Lopes, A. Nichau, M. Schnee, S. Lenk, A. Besmehn, K.K. Bourdelle, Q.T. Zhao, J. Schubert and S. Mantl, IEEE Electron. Dev. Lett., 32 15 (2011).
2 I.P. Tyagulskii, S.I. Tyagulskii, A.N. Nazarov, V.S. Lysenko, K. Cherkaoui, P.K. Hurley, Microelectronic Engineering, 109 31 (2013).
3. I.P. Tyagulskyy, I.N. Osiyuk, V.S. Lysenko, A.N. Nazarov, S. Halb, O. Buiu, Y. Lu, R. Potter, P. Chalker Microelectronics Reliability, 47 726 (2007).
4. V.S. Lysenko, T.N. Sytenko, V.I. Zimenko, I.P. Tyagulskyy, O.V. Snitko, I.N. Osiyuk, A.N. Nazarov, T.E. Rudenko, Solid State Commun., 57 171 (1986).