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W CMP Initiation Mechanism Study Using in-Situ Metrologies
The purpose of this work is to reveal the mechanism behind the low initial rate by using various in-situ metrologies on an Applied Materials CMP system [4].
EXPERIMENT
Different W films with varied morphologies were deposited under different deposition conditions using the Applied Materials Centura® system. W morphologies were characterized using Applied Materials SEMVision™. W films were then polished on an Applied Materials Reflexion®LK, using Cabot microelectronics W slurries (A and B with different abrasive types). During polish, optical reflectivity and real-time W thickness measurements were collected in-situ. Polish was stopped at different times and W film surface morphologies were studied and compared using a SEM field of view (FOV) of 1µm.
RESULTS
CVD W film has a rough surface. The degree of roughness is affected by atomic layer deposition (ALD) W precursor types and other deposition conditions. The larger the W grain size, the longer it took for polishing to transit the low rate initiation period as demonstrated by in-situ W thickness monitoring metrology when the film was polished using slurry A. This phenomenon was further confirmed with W slurry B using in-situ optical reflectivity metrology, in-situ W thickness metrology, and SEM images of W film surface morphologies. During the initiation period, optical reflectivity increased with polish time, then reached a stable value, indicating that the process of grain planarization was the root cause of the low initiation rate. W film with larger grain size had lower optical reflectivity and required more time to planarize the grain; the initiation time was also longer. It was not until the grain was planarized that the W film and polishing pad could make full contact and achieve high and stable friction to produce a high and stable removal rate. This study suggests that any removal rate study of W CMP should take into account the initiation: it is important to use consistent polish time and W film with consistent mophology to compare removal rates among different processes.
REFERENCE
1. Dick James, “Intel’s 22-nm Tri-gate Transistors Exposed,” http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/intels-22-nm-tri-gate-transistors-exposed/, April 23, 2012
2. W.A. Kneer et.al., J. Electrochem. Soc., 144 (9), 3041, 1997.
3. Y. Seo et. al., Mat. Sci. and Eng. B 118281, 2005.