(Invited) Microwave-Based Metrology Platform Development: Application of Broad-Band RF Metrology to Integrated Circuit Reliability Analyses

Wednesday, May 14, 2014: 08:40
Union, Ground Level (Hilton Orlando Bonnet Creek)
L. You, C. A. Okoro, J. J. Ahn, J. J. Kopanski, and Y. S. Obeng (NIST)
Three dimensional stacked integrated circuits (3D-ICs), achieved using through-silicon vias (TSV), is an enabler for the continued miniaturization, increased performance and functional diversification of microelectronic devices. However, their introduction to the market has been hindered by many reliability challenges; in particular, stress related failures in this new technology are significantly worse than the traditional planar integrated circuits. For example, the large mismatch in the coefficient of thermal expansion (CTE) of the silicon matrix (~2.3 ppm/ºC) and the copper TSV (~17 ppm/ºC) interconnects, results in the buildup of stresses. This introduces a new reliability challenges such as the degradation of transistors and other front-end-of-line (FEOL) devices, in close proximity to the TSVs [2].

By and large, stress is the root cause of most microelectronic devices reliability failures; it has been reported that 65% of all microelectronic device failures are thermo-mechanical related, mostly due to thermally induced stresses and strains stemming from the mismatch in the neighboring dissimilar materials [1]. The stress evolution leads to stress buildup, resulting in the generation of defects such as cracks, voids, delamination, plastic deformation, warpage and buckling. These damages could ultimately lead to open or short circuits in the microelectronic chip, resulting in their failure.

Metrology for accurate understanding and quantification of the impact of stress evolution in 3D-ICs structures is key to addressing stress-related reliability challenges associated with the 3D-IC technology. In this presentation, we discuss our attempts to identify and characterize types of performance-limiting defects in three-dimensional (3-D) nanoelectronic devices, with special focus on 3-D interconnects, and relate the defects to the evolution of stress, where and why they form within the samples studied. In addition, we discuss non-destructive techniques for identifying such performance-limiting defects, without interrupting the responsible mechanistic phenomena [3]. 


  1. B. Wunderle, B. Michel et al, “Progress in Reliability Research in the Micro and Nano Region.” Microelectronics and Reliability, Vol. 46, pp. 1685-1694.
  2. A. Mercha et al, Comprehensive Analysis of the Impact of Single and Arrays of Through Silicon Vias induced Stress on High-k / Metal Gate CMOS Performances”, International Electron Devices Meeting (IEDM), Dec. 2010, San Francisco, CA, USA, pp. 2.2.1 -2.2.4.
  3. C. Okoro et al., “Accelerated Stress Test Assessment of Through-Silicon Via using RF Signals,” IEEE Transaction on Electron Devices.  Vol. 60, No.6, 2013,  pp 2015-2021