(Invited) Metrology for 3D Integration

Wednesday, May 14, 2014: 08:00
Union, Ground Level (Hilton Orlando Bonnet Creek)
R. A. Allen (NIST), V. Vartanian (SEMATECH), D. Read (Boulder, Colorado), and W. Baylies (Baytech)
Three-dimensional stacked integrated circuits (3DS-IC) fabrication requires complex technologies such as high-aspect ratio through-silicon vias (TSVs), wafer thinning, thin wafer handling and processing, and bonding of thin wafers with complex patterned surfaces. The implementation 3DS-IC also presents significant metrology challenges. This talk will give an overview of the metrology needs for 3DS-IC, identify solutions, and describe work towards the development of standards to support the 3D ecosystem. 

One of these standards under development is investigating methods for identifying and characterizing voids between bonded wafers. Wafer bonding in a 3DS-IC process is typically an intermediate step. After bonding, one or both of the wafers will undergo processes such as thinning, thin film deposition, lithography, and patterning. The presence of voids between the wafers will cause significant stack thickness variation, which can lead to failure at one or more of these steps. A number of tools can be used to identify and/or characterize voids; this standard will provide members of the 3DS-IC community with guidance for choosing the tool or tools that will best address the specific need. 

Preliminary results from a round robin experiment, involving approximately 20 laboratories, will be shown.  This experiment uses as a test structure a bonded wafer pair with a number of voids patterned into one of the wafers before bonding.  The sizes of the programmed voids range from 0.5 μm to 300 μm with depths of 15 nm to 1200 nm and are placed in isolated, semi-dense, and dense patterns.  A scanning acoustic microscope image of one instance of the test chip with patterned voids is shown in the figure.