(Invited) Replacement Metal Gate/High-k Last Technology for Aggressively Scaled Planar and FinFET-Based Devices

For (sub-)22nm nodes, new device architectures such as multi-gate FinFET-based devices have long been regarded an attractive option to allow further CMOS scaling thanks to their improved electrostatics and reduced V_T-variability [1]. In this work, we address the need for processes compatible with their 3D-architecture by reporting on a novel EWF engineering approach [2] which enables wide V_T-modulation (>500mV ΔV_T in narrow fin (W_Fin≥5nm), triple-gate FinFETs in Fig. 1), with no EOT nor J_G penalty, improved mobility and BTI, excellent mismatch performance, up to ~6.3× reduced noise (Fig. 2), and minimized parasitic R_gate and σ(R_gate), while suitable also for scaled planar FETs where larger EWF shifts from mid-gap to reach low or high-V_T targets are needed. It relies on diffusion mechanisms in the gate stack, namely controlled Al diffusion from the fill-metal (Co_xAl_y) through an ultra-thin TaN layer into the TiN covering the high-k dielectric (e.g., HfO₂), and fine-tuned TiN/TaN thicknesses. Since Al-rich TiN has a more n-type EWF, stacks with higher amount of Al diffused into TiN translate into lower EWF values (→ lower NMOS V_T), with TiN growth optimized for enhanced (NMOS) or inhibited (PMOS) Al diffusion into/through it.

Focusing next on gate dielectric scaling, we report a thorough evaluation of the impact of HfO₂ doping [3], post high-k deposition thermal (PDA) and SF₆-based plasma treatments [4,5] for planar vs. FinFET devices with different Si crystal orientations for the fin top and sidewall surfaces, providing a deeper insight into underlying degradation mechanisms. Higher k-value HfO₂ (k~30) is achieved by introducing a metallic dopant during HfO₂ growth, followed by an 800°C PDA which crystallizes HfO₂ into its cubic phase. Up to 10³× J_G reduction at ~9.7Å EOT and net performance (I_ON) and reliability (BTI, TDDB) improvements when normalized to J_G make this material attractive for low-power applications. F incorporation into the gate stack through exposure of HfO₂ to a SF₆-plasma results in substantially reduced N_it and noise values, improved mobility, and no EOT penalty down to narrow fin devices (W_Fin≥5nm), mitigating the impact of fin patterning, fin corners and fin sidewalls crystal orientations due to defects passivation by Hf-F and Si-F bonds formation. The plasma was optimized by increasing the number of ions reaching the bottom of narrow, high aspect-ratio gate trenches such that it can be used to incorporate F in the gate stack and to selectively remove the p-EWF/barrier metals (TiN/TaN) from NMOS areas in a simplified, highly scalable dual-EWF metal CMOS scheme [5] suitable for 2D and 3D device architectures and which maximizes the space for gate metallization. NBTI lifetime improvement with SF₆ at 125°C is however fairly modest in the (sub-)1nm EOT regime, substantially increasing upon PDA introduction in the process flow, and for higher PDA temperatures (760°C→800°C). PDA devices exhibit reduced J_G (enabling nFETs with ~10× lower J_G at given V_T) and show considerably smaller total effective trap density values, despite an increase in N_it (~1.4-1.8×), thanks to reduced bulk traps/defects. The latter seem thus to play a key and dominant role in NBTI for ultra-thin EOT, being mostly pre-existing defects contributing to charge trapping and de-trapping during stress and relaxation as inferred by the larger recoverable (R) vs. permanent BTI degradation components, calculated assuming universality of relaxation. Less steep R vs.stress time dependence in PDA devices also indicate less generation of new defects during stress, with improved hot-carrier immunity due to less charge trapping into bulk defects corroborating reduced presence of the latter. Further reliability gain is obtained for PMOS with (100) fin sidewalls in agreement with LF-noise results (Fig. 2).

References

[1] C. Auth et al., VLSI Tech. Dig., p.131 (2012);

[2] A. Veloso et al., VLSI Tech. Dig., p.194 (2013);

[3] L.-Å. Ragnarsson et al., VLSI Tech. Dig., p.27 (2012);

[4] A. Veloso et al., VLSI Tech. Dig., p.33 (2012);

[5] A. Veloso et al., SSDM Tech. Dig., p.590 (2013).