Through silicon vias (TSV) are copper (Cu) interconnects used in three dimensional integrated circuits (3D-IC) and other packaging to allow inter-chip communication. Since Cu is anisotropic, understanding the evolution of microstructure in TSVs is of major importance as it can influence the Cu’s electrical properties, such as resistance and electro-migration resistance, as well as mechanical properties. These properties can affect the materials response to thermo-mechanical stresses undergone by Cu-TSVs. Microstructural studies have focused on isothermal holding temperatures and times to imitate fabrication conditions [1-3], however, in-use
conditions, which are typically of lower temperatures and higher frequencies to replicate thermal cycling over a chip’s lifetime, have not been greatly explored. This study correlates simulated in-use cycling parameters, such as cycling temperature and number of cycles, to microstructural changes, specifically grain size, observed in the Cu of TSVs. Silicon (Si) chips containing blind Cu-TSVs underwent 2000 thermal cycles from room temperature to maximum temperatures of 100 °C, 150 °C, or 200 °C. Grinding, polishing, and focus ion beam (FIB) milling were used to cross-section the TSVs and provide sufficient surface quality for electron backscattering diffraction (EBSD) to evaluate microstructural changes from thermal cycling. The average grain size remained around 3 μ
m and no significant differences were documented for average grain sizes along the length of TSVs before and after cycling. Furthermore grain size distribution also, showed little change with peaks around 1 μ
m for samples containing minimal voiding and approximately 2.5 μ
m for samples with significant pre-existing voids. While the low cycling temperatures used in this study are indicative of the conditions used in a majority of applications, they are too low to activate grain boundary migration and cause much microstructural changes in the Cu-TSVs.
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2. A. Heryanto, W. N. Putra, A. Trigg, S. Gao, W. S. Kwon, F. X. Che, X. F. Ang, J. Wei, R. I Made, C. L. Gan and K. L. Pey, Journal of Electronic Materials, 41  2533-2542 (2012).
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