Ultrathin (8-14 nm) Conformal SiN for sub-20 nm Copper/Low-k Interconnects

Monday, May 12, 2014: 10:40
Flagler, Ground Level (Hilton Orlando Bonnet Creek)
S. V. Nguyen, D. Priyadarshini, H. K. Shobha, T. J. Haigh (IBM at Albany Nanotech), C. K. Hu, S. A. Cohen, E. Liniger, T. M. Shaw (IBM T.J. Watson Research Center), E. D. Adams, J. Burnham (IBM Essex Junction), A. Madan, N. R. Klymko (IBM Semiconductor R&D Center), C. Parks, D. Yang, S. E. Molis (IBM Semiconductor Research and Development Center), Y. Lin (IBM at Albany Nanotech), G. Bonilla, A. Grill, D. Edelstein (IBM T.J. Watson Research Center), D. F. Canaperi (IBM at Albany Nanotech), L. Q. Xia, S. Reiter, M. Balseanu, and M. Y. Shek (Applied Materials)
Ever since Al(Cu) wires were replaced by Cu to reduce RC delay, the development of lower k dielectric materials has been a challenge to the back end of line (BEOL) process [1,2]. Copper wiring with low-k or ultra low-k (ULK) dielectrics for high-performance CMOS IC’s requires the use of a robust dielectric cap barrier to prevent inter- and intra-level Cu diffusion and also to maintain device yield and reliability. Plasma Enhanced Chemical Vapor Deposited (PECVD) low-k SiCNH and SiN are the predominant dielectric Cu diffusion caps used by the industry, in part due to the strong cap/Cu debond energies [3]. This paper will present the ultrathin (<15 nm) cyclic conformal multilayer SiN dielectric as potential dielectric caps and liner for capacitance reduction in sub-20nm Cu-Low k interconnect.
We developed a new cyclic multilayer conformal ultrathin (8-14 nm) SiN deposition process to improve Cu CMP recess step coverage. This process includes cyclic low rf power plasma deposition of nano thick (~2 nm) SiN using Silane and Ammonia gases and then subsequent variable rf plasma power Nitrogen (N2) plasma treatment to minimize Cu sputtering and diffusion. The process is repeated in a cyclical manner until desirable film’s thickness is achieved, figure 1. The film deposition step and it enhanced STEM and EDX step coverage images for the post-CMP top corner Cu recess divot structure as showed in figure 2. The Triangular Voltage Test (TVS) and oxidation barrier (310 C, 24 hr exposure in air) evaluation showed this thin (10-14 nm thick ) SiN cap is a good oxidation and Cu barrier. Optimal cyclic SiN film has higher breakdown voltage and lower low leakage than standard SiCNH cap, even after exposure to UV cure, figure 3. As deposited, the SiN film has compressive stress in 500 MPa range. After UV direct UV exposure for 180 sec at 380C, the film’s stress still retain at 300 Mpa compressive. The cyclic SiN cap has excellent modulus of 159 GPa and hardness of 24 GPa. BEOL 80 nm pitch device electrical data showed that device reliability of the 10-12 nm SiN cap film are about comparable to standard 25 nm SiCNH cap but with significant lower device capacitance.
A new generations of ultra-thin (<15 nm) conformal cyclic SiN dielectric cap with robust electrical, mechanical and oxidation barrier performance was developed for sub-20 nm Cu-Low k interconnect potential use as cap and liner.
Acknowledgments: This work was performed by Alliance Teams at various IBM Research and Development Facilities and at University at Albany Nanotech Foundation.
[1]Y. Ushiki et al., Proceeding of the VLSI Multilevel Interconnection, (1990) pp. 413
[2] S. P. Jeng et al., Proceeding of Advanced Metallization for Devices and Circuits, (1994) pp. 25.
[3] J. R. Lloyd et al., IEEE Transaction on Devices and Materials Reliability, vol. 5, no.1, pp.113-118, March 2005.