(Invited) Resistive Switching and Current Status of HfO2-based RRAM

Tuesday, May 13, 2014: 16:50
Taylor, Ground Level (Hilton Orlando Bonnet Creek)
C. Walczyk, M. Sowinska, D. Walczyk, P. Calka (IHP), and T. Schroeder (IHP, IHP)
Recent advances in the performance of resistive random access memory (RRAM) have engendered significant interest for system-on-chip (SoC) applications in Si-based CMOS technologies1, including various wireless sensor networks (WSNs) and medical health care devices. For most applications, the realization of energy-efficient sensor nodes with a high lifetime provides the prospect of completely autonomous systems. Recent hardware-based approaches to obtain energy-efficient sensor nodes focus on the integration of RRAM in a microcontroller unit (MCU) 2.

Given the wide range of possible transition metal oxides, HfO2-based RRAM provides an ideal CMOS back-end-of-line (BEOL) compatibility with sufficient performance parameters and thus considerable progress has been made in integrating RRAM devices as well as in understanding the physical/chemical properties of the resistive switching behavior3,4. It still remains difficult in HfO2-based RRAM to further reduce energy dissipation and in addition to increase reliability for autonomous sensor nodes. To address this issue, RRAM integration aspects are accompanied by fundamental materials research studies.

First, non-destructive and in-operando Hard X-ray Photoelectron Spectroscopy (HAXPES) 5,6 (Fig. 1(a)) was performed to correlate the RS characteristics for increased current compliance (CC) with materials modifications at the HfO2/Ti interface. HAXPES data indicate that the RS behvior does not only affect the Ti 2p, Hf 4f and O 1s photoemission lines but also C 1s (Fig. 1(b)). After survey spectra normalization to the Hf 4d peak intensity, the C 1s peak intensity increases with the increase of the electrical stress applied to the sample. After electroforming, the C 1s to Hf 4d intensity ratio IC/IHf increases from 0.4 (as-deposited-state) to 0.6 (ON-state 30 mA CC). This result indicates that carbon present in the HfO2film cannot be neglected and its role on the RS behavior of RRAM cells should be investigated in more detail. Obtained results will be presented.

The fundamental materials research insights were then transferred to integrated 4 kbit RRAM test modules with the associated control circuitry 5 (Fig. 1(c)). Due to the statistic nature of the electroforming process as well as due to process-induced variation, the inter-cell variability of memory elements in a memory array after electroforming and during RS must be studied. To address the point above, Fig. 1 (d)-(e) shows the current distribution in the initial state (d) and after DC forming (e) for one 64 × 64 bit (4 kbit) memory device array. We note that the initial state shows inter-cell variability which affects the DC forming process. Statistical analysis reveals that some memory elements were conductive with a current of >1×10−5A and could thus not be formed. The presentation will summarize further results on inter-cell and intra-cell variability for a 4 kbit memory array.

This work is financially supported by the German research foundation DFG under contract SCHR1123/7-1.

[1] J. Suhonen et al. Low-Power Wireless Sensor Networks, Springer, (2012).

[2] Y. Zhang, Future Wireless Networks and Information Systems, Springer, (2012).

[3] S.-S. Sheu et al., Proc. ISSCC, pp. 200–202, (2011).

[4] Tz-Yi Liu et al., Proc. ISSCC, pp. 210–212, (2013).

[5]M. Sowinska et al., Appl. Phys. Lett. 100, 233509 (2012).

[6] T. Bertaud et al., Appl. Phys. Lett. 101, (2012).

[7] D. Walczyk et al., ISCDG, pp. 143-146, (2012).

Figure 1: (a) RRAM device mounted on a PCB inside the HAXPES vacuum chamber 5,6. (b) HAXPES survey spectra for different resistive states: as-deposited and three ON-states (CC = 6, 20 and 30 mA). C 1s spectra of the as-deposited- and ON-state (30 mA). (c) Image of the 4 kbit memory array with control circuits 7. Current distribution in the initial state (d) and after DC forming (e) for a 64 × 64 bit (4 kbit) memory device array.