Lateral Gemanium Growth for Local GeOI Fabrication
Lateral Ge growth is carried out by using a single wafer reduced pressure CVD system. For sample preparation, epitaxial Si is deposited. The thickness of the Si on buried oxide (BOX) is targeted to 430 nm. Then wet oxidation for 300 nm is performed to produce a 300 nm thick SiO2 cap on top of 300 nm thick Si on the BOX. Top SiO2 and Si on BOX are removed by RIE dry etching to form lateral Si (010) or Si (110) surfaces at the sidewall of a mesa structure. After that, the wafer is cleaned by standard HF-last RCA cleaning. The wafer is loaded into the epi. chamber and baked at 850oC in H2 to remove residual oxide on the Si sidewalls. Then selective etching of Si by HCl is performed to form a cavity in the SiO2. After the HCl etching, Ge is deposited selectively using a H2-GeH4-HCl gas mixture. SEM is used for characterization of the deposited Ge and TEM is applied for dislocation analysis. The strain distribution is analyzed by micro Raman spectroscopy at 514 nm laser wavelength.
An angle view SEM image of the sample after HCl etching is shown in Fig. 1. By HCl etching Si between the BOX and the SiO2 cap is laterally removed. The thickness loss of the BOX and the SiO2 cap are negligible indicating that the Si etching process is highly selective to SiO2. No bending is observed at the floating part of the SiO2 cap layer. At the etchfront a Si (111) facet is formed by the lateral HCl etching.
A cross section TEM image of the sample after HCl etching and selective Ge growth is shown in Fig. 2. The Ge layer is selectively grown laterally on the Si surface in the cavity formed by the HCl etching. Dislocations are densely located near the interface between Si and Ge. Aspect ratio trapping (3) also works for the lateral direction, resulting in a high crystal quality Ge layer growth after ~200 nm.
In Figure 3, an AFM amplitude image of a 5 µm square mesa structure with  sidewall direction is shown after HCl etching and lateral Ge growth followed by the removal of the SiO2 cap by HF dip. The interface between Si and Ge is visible. The root mean square of the Ge surface roughness is ~0.4 nm. It is defined by the interface roughness between Si and the SiO2cap layer.
In Figure 4, a plan-view TEM image of a 5 µm square mesa structure after HCl etching and lateral Ge growth is shown. A (113) facet is observed at the growthfront of Ge. Dislocation networks are located near the Si interface. Stacking faults run only parallel or perpendicular to the  direction. Between them a wide area without any dislocations toward the  direction is observed.
These results demonstrate the feasibility of the fabrication of local GeOI with high crystal quality by an additional lithography and an etching process.
1) Y. Yamamoto et al., Solid-State Electronics 60 (2011) 2
2) Y. Yamamoto et al., Thin Solid Films 520 (2012) 3216
3) J. S. Park et al., Appl. Phys. Lett. 90 (2007) 052113