(Invited) Challenges and Developments in GeSn Process Technology for Si Nanoelectronics

Sn-related group-IV semiconductor such as Ge_1-xSn_x and Ge_1-x-ySi_xSn_y are one of the most attractive materials for Si nanoelectronic applications. Ge_1-xSn_x alloy is expected to be a stressor for strain-engineering material of Ge devices [1,2]. In addition, Ge_1-xSn_x with a Sn content approximately higher than 10% is a direct transition semiconductor material, and that allows us to use electrons of the conduction band at the G-point for electronic applications. Those promise to improve on the performance of Ge devices and to introduce new functions of transistors, light receiving/emitting element, photovoltaic cells, etcon Si nanoelectronics.

In these several years, we have investigated the crystal growth of Ge_1-xSn_x and Ge_1-x-ySi_xSn_y thin films and the crystalline and electronic properties [2-5]. In addition, we have recently investigated and developed Ge_1-xSn_x technologies for electronic applications; those are (1) crystalline and electronic properties of defects, (2) strain and energy band engineering, (3) impurity doping, (4) metal/insulator/semiconductor (MOS) gate-stack structure, (5) metal/semiconductor (MS) contacts. In this report, we will present recent achievements in our research of Ge_1-xSn_xtechnology.

Defects in Ge_1-xSn_x alloy

It is known that a vacancy in Ge is an acceptor-like defect and undoped Ge grown at low temperature often shows p-type conduction. The formation and behavior of defects in Ge_1-xSn_x alloy should be essentially understood for electronic and optoelectronic applications. We investigated the influence of Sn on the electronic properties of Ge_1-xSn_x by preparing metal/Ge Schottky diodes with Sn-ion implantation and measuring the deep-level transient spectroscopy (DLTS) [6]. The Sn-ion implantation with a dose of 10¹⁴ cm^-2 and a acceleration voltage of 370 kV generates acceptor-like defects in Ge substrate with a hole-concentration of 10¹⁷ cm^-3, and these defects is hardly annihilated even after annealing as high as 500 °C. Also, we found by DLTS measurement that the concentration of vacancy-related deep-level defects can be reduced with Sn-implantation, although some additional Sn-related defects are formed.

Oxidation of Ge_1-xSn_x and gate-stack structures

It is essentially important to investigate the oxidation behavior of Ge_1-xSn_x for engineering the Ge_1-xSn_x gate-stacks. We previously reported the electrical properties of Al₂O₃/Ge_1-xSn_x/Ge MOS capacitors [7]. Recently, we examined the oxidation of Ge_1-xSn_x layers pseudomorphically grown on Ge substrate and investigated the behavior of Sn segregation during oxidation [8]. We found the surface segregation of Sn atoms near the Ge_1-xSn_x surface by oxidation at 400 °C. Thermal oxidation of Ge_1-xSn_x causes the Sn diffusion from Ge_1-xSn_x and the formation of Sn oxide on the surface. The capacitance-voltage measurement of Al/Al₂O₃/Ge_1-xSn_x capacitors also reveals that the oxidation of Ge_1-xSn_x increases in the concentration of holes unintentionally generated from acceptor-like defects in Ge_1-xSn_x layers. We need to develop the defect control technology for gate-stack formation of Ge_1-xSn_xwith considering Sn behavior during oxidation and annealing.

Metal/Ge_1-xSn_x contact formation

The formation of metal/Ge contacts with low parasitic resistance is required to improve on the performance of Ge devices. We examined the formation of NiGe/Ge_1-xSn_x contacts with germanidation processes of Ni/Ge_1-xSn_x system [9]. A single layer of Ni mono germanostanane, Ni(Ge_1-xSn_x) can be formed by annealing Ni/Ge_1-xSn_x/Ge samples at 350~550 °C. We found that the Sn content in Ni(Ge_1-xSn_x) increases with the Sn content of Ge_1-xSn_x and that decreases with the annealing temperature due to the Sn segregation from Ni(Ge_1-xSn_x). Smooth surface of Ni(Ge_1-xSn_x) layers on Ge_1-xSn_x can be successfully obtained with annealing at as low as 350 °C even for a Sn content as high as 6.5%, although the agglomeration of Ni(Ge_1-xSn_x) grains severely occurs after annealing at higher than 550°C.

In summary, the incorporation of Sn promises additional key factors for engineering strain, energy band structure, interface, and defects in Ge nanoelectronics. We need to develop the crystal growth, process, and device technologies based on deeply understanding the crystalline and electronic properties of Sn-related group-IV semiconductor materials.

Acknowledgements

This work was partially supported by a Grant-in-Aid for Specially Promoted Research of MEXT and an ALCA Program of JST in Japan.

References

[1]     S. Takeuchi et al., APL 92, 231916 (2008).

[2]     S. Takeuchi et al. ECS Trans. 33, 529 (2010).

[3]     O. Nakatsuka et al. ECS Trans. 58, 149 (2013).

[4]     S. Zaima et al., ECS Trans. 50, 897 (2012).

[5]     S. Zaima et al., ECS Trans. 41, 231 (2011).

[6]     T. Arahira et al., Ext. Abstr. of Int. Conf. on SSDM2013, p. 620, 2013.

[7]     C. Merckling et al., Appl. Phys. Lett. 98, 192110 (2011).

[8]     K. Kato et al., in Abstr. of IWDTF2013, p. 99, 2013.

[9]     T. Nishimura et al., Solid-State Electronics 60, 46 (2011).