Surface Inspection of Cu-Cu Non-Thermal Compression Bonding for Wafer-to-Wafer 3D Stacking

Backside illuminated CMOS image sensors with a 3D stacked architecture, where the pixel array is attached on top of the logic circuit, was introduced and have just come to the market. Image sensor featuring 3D stacking was realized by connection between the interconnect layers of the top and bottom parts using vertical type through-silicon via (TSV).¹

Cu bonding technology for 3D integration has been studied and widely applied.²As Wafer-to-wafer bonding process is now being used widely and matured through the production of Backside illuminated CMOS image sensors, Copper-copper bonding provides an attractive route to 3D stacked image sensor since it creates a strong metal bond and enables vertically electrical connection during the bonding process.

Specific pre-bonding surface conditioning is necessary to insure high bonding quality of patterned Cu wafers using Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking. Surface preparations for the hybrid fusion bonding such as removal of Cu oxide, Cu surface protection and optimized CMP planarization patterned Cu surfaces have been studied,³ but the study on plasma condition for hybrid fusion bonding is relatively a few. The work described here is investigating of the plasma-related Cu patterned hybrid surface preparation under different plasma conditions.

The main physical mechanisms about Cu-Cu non thermal compression bonding are spontaneous adhesion of hydrophilic surfaces followed by Cu diffusion across the bonding interface when Cu-Cu contact is reached (diffusion bonding) have been previously reported.⁴

The property of Cu dielectric diffusion barriers used in ULSI is hydrophobic. For the efficient bonding of hydrophobic-hydrophobic layers, surface conversion process is introduced.⁵

In the case of Cu-patterned hybrid bonding in typical Cu metallization layer in ULSI, Trade-off between dielectric diffusion barrier and Cu cannot be avoidable by surface conversion process.

During the Cu-patterned hybrid bonding development, the common electrical failed areas were found.

To investigate the failure mechanism, influence of plasma condition on the activation of wafer surface and bonding quality was studied. The wafer surface was examined by X-ray photoelectron spectroscopy (XPS), surface roughness, and observation of differential work function uniformity over a full wafer area caused by plasma-induced charge.⁶The ChemetriQ NVD inspection system from Qcept Technologies was used to inspect differential work function uniformity.

After implementing plasma treatment applied in bonding process, Non-uniformity of a charge map and different plasma influence over a full wafer area were shown, even there was no difference through the AFM analysis. For the optimization of the bonding process, especially plasma process, a method to examine the surface condition in this paper makes it possible to monitor the plasma process and improve bonding process

References:

[1] S. Sukegawa et al., “A 1/4-inch 8Mpixel Back-Illuminated Stacked CMOS Image Sensor” ISSCC, pp 484-485, 2013

[2] Y. Tang et al.,“Wafer-level Cu–Cu bonding technology” Microelectronics Reliability. 52 (2) pp312-320, 2012

[3] B. Rebhan et al.,“Low-Temperature Cu-Cu Wafer Bonding” ECS Transactions, 50 (7) pp139-149, 2013. S. Farrens et al., “Metal Surface Preparation with Point of Use Wet Chemistry” ECS Transactions, 33 (4) pp17-26, 2010. D. F. Lim et al., “Surface Passivation of Cu for Low Temperature 3D Wafer Bonding” ECS Solid State Lett. 1 (1) pp11-14, 2012, L. D. Cioccio et al., “An Overview of Patterned Metal / Dielectric Surface Bonding: Mechanism, Alignment and Characterization” ECS Transactions, 33 (4) pp3-16, 2010

[4] P. Gueguen et al., “Copper Direct Bonding: an innovative 3D interconnect” presented at ECTC 2010

[5] A.Usenko et al., “Silicon Nitride Surface Conversion into Oxide to Enable Hydrophilic Bonding” ECS Transactions, 33 (4) pp475-483, 2010

[6] R. Spicer et al., “Controlling Process-Induced Heightens Productivity” Semiconductor International March pp2-6, 2009