Precipitation Behaviors of Rapid Thermal Annealing Treated Silicon Wafers under Various Thermal Cycles

Monday, 6 October 2014: 15:20
Expo Center, 1st Floor, Universal 17 (Moon Palace Resort)
D. Lee (SunEdison Semiconductor), T. Kim, S. Park, T. Kim, Y. Lee, E. Park, H. Yeo (MEMC Korea), and R. Falster (MEMC Electronic Materials, Spa)
For decades, oxygen precipitates in Cz silicon wafers have been a subject of defect engineering to optimize device yields and performance at both current high volume manufacturing and future generation nodes.  With the ability of precipitates capturing metallic impurities, a well controlled built-in intrinsic gettering (IG) provides a self-insurance protecting fabs from suffering unexpected yield loss caused by metal contamination outside the control limit [1]. Such IG sinks traditionally are created, either by RTP or conventional furnace heat treatments, quite deep in the bulk, resulting in a wide denuded zone (DZ).  This scheme has worked perfect for most devices with monolithic integration as fast diffusing metals travel the distance equal to the DZ depth quite easy. However, the industry is increasingly adopting 3-D integration, stacking multiple chips vertically using through Si via (TSV) techniques. Multichip stacking requires each die to be thinned substantially by back grinding down to 50um or even <30um, depending on the number of stacked dies. This results in either complete or major loss of IG sinks along with the bulk removal of the wafer. In this respect, IG with a shallower DZ is desired so that a sufficient amount of IG sinks are retained even after extensive thinning. On the other hand, the effect of oxygen precipitation on the yield strength is increasingly receiving attention as photolithography overlay is becoming more sensitive to local deformation [2]. A precisely controlled high density of precipitates would be desirable in this regard.

In this report, we demonstrate that a 2-step Rapid Thermal Annealing (RTA) treatment in NH3 and Ar gas is capable of producing a high density of precipitates in an extremely uniform profile in the 300mm silicon wafers under CMOS-like thermal cycles. The RTA treatment is a special variant of MDZ® that has been widely adopted in the industry for >10 years [1, 3]. Figure 1 shows typical depth profiles of precipitates in the high oxygen material after through a CMOS thermal simulation and after a subsequent extra growth cycle. Adding the extra growth cycle was necessary for the sake of ensuring all the existing precipitates to be detectable as the metrology tool (laser scattering tomography) would otherwise miss those sub-threshold size in the count, especially in the case of the lower oxygen concentration material. Quite a uniform density of precipitates is formed at the depth of around 7 microns and extended to the entire thickness of the wafers with the maximum density around 8x109/cm3 and 7x109/cm3 in the cases of higher and lower oxygen concentration materials, respectively. It can also be seen that in the case of higher oxygen material the full cycle of the D simulation has effectively grown the precipitates so about 70% of the precipitate distribution was detectable without going through a growth cycle (the D2 curve). These results are pretty consistent with the previous work reported by co-authors, where the uniform density of precipitates is explained as a result of the nitride layer blocking vacancy sinking to the wafer surface [4]. The precipitation sites are created by vacancy aggregation in the course of fast post-RTA cooling. 

The radial distribution of oxygen precipitates is remarkably uniform, as shown in Fig. 2 (a) and (c). In comparison, the as-grown wafers (b and d) resulted in a large variation, especially in the high oxygen material, which is due to the inhomogeneous distribution of point defects formed during crystal growth. The result clearly demonstrates that the 2-step RTA eliminated the crystal originated variability, very effectively.

In summary, adding a 2-step RTA treatment produces a high density precipitates near surface, uniformly both vertically and laterally, guaranteeing a <20um thick layer of IG sinks to be retained even after through wafer thinning to 30um. 


[1] K. Bae, .J. Kim, Y. Hong, S. So, S. Lee, S. Kim, S. Ha, C. Koh, S. Pyi and D.M. Lee, ECS Proc. Vol. 2 “Semiconductor Si,”. Eds. H. Huff et al, 786 (2002)

[2] T. Ono, W. Sugimura, T. Takayuki and M. Hourai, ECS Trans. 2, 109 (2006).

[3] R. Falster, Future Fab International, 12, 240, (2002)

[4] V. Voronkov, R. Falster, T. Kim, S. Park, T. Torack,, J. Appl. Phys. 114, 043520 (2013) (1999).

[5] V. Voronkov and R. Falster, J. Cryst. Growth 204, 462