Cryoetching of Silicon and Advanced Materials for 3D Interconnects
Several different processes are commonly exploited for deep silicon etching. One of the techniques is the so-called cryogenic process, which requires the substrate to be cooled down to a temperature of the order of ‑100°C. Since its introduction by a Japanese team in the end of the eighties, the cryoetching process has been studied by different groups and has been used to etch silicon in a wide range of dimensions from several dozens of nanometer to hundreds of micron-wide structures. The typical cryoetching process relies on plasma which is composed of SF6 and O2. In the plasma, an SiOxFy passivation layer is generated on the vertical sidewalls of the etched features. One of the great advantages in cryoetching process is that any specific post etch treatments are not required because a passivation layer evaporates at ambient temperature. Hence, the surface of micro- or nanostructures fabricated by cryoetching are clean. The most critical point of cryogenic etching is the control of the passivation layer which determines the etching profile. However, it is very difficult to characterize this passivation because of its unique nature, as mentioned above. Consequently, the passivation layer characterization has to be carried out in-situ at a cryogenic temperature.
In this paper, we will detail in-situ experiments including mass spectrometry, ellipsometry, double cavity tests and XPS, which were performed in order to investigate physical and chemical mechanisms involved in the silicon cryoetching process. We will also show that etch by-products (SiF4) can participate in the passivation layer formation and reinforce it. Cyclic processes are desired in order to enhance the robustness of the cryoetching process. Among them, the so-called STiGer process consists in alternating SiF4/O2 deposition regime and SF6 etching regime. This particular process greatly enhances process reproducibility. In addition to deep silicon, cryoetching was applied to interconnects in back-end-of-the-line part of advanced CMOS technology, focusing on the etch of organosilicate (OSG) low-k materials with different porosities. The objective is to minimize the plasma induced carbon depletion. We defined an equivalent damaged layer (EDL) by ellipsometry and FTIR experiments, and measured the change of dielectric constant. Etching experiments were performed on patterned and blanket wafers. In porous low-k materials, pores can be filled with the introduced chemicals and/or etch by-products so that plasma-induced damage is significantly reduced. Although the passivation layer evaporates at ambient temperature, condensate by-products (carboxylic acids) remain stable up to room temperature. However, this condensate can be removed easily by high-temperature annealing without additional damage to the low-k materials.