Through Silicon Via II

Tuesday, 7 October 2014: 08:00-12:40
Expo Center, 1st Floor, Universal 13 (Moon Palace Resort)
Chairs:
Shoso Shingubara and Mitsumasa Koyanagi
08:00
1684
Recent Progress in Cu Electrodeposition for TSV (Through Silicon Via)
J. J. Kim, M. J. Kim, S. Choe, K. H. Kim, H. C. Kim, and A. Lee (Seoul National University)
08:40
1685
Kinetic Monte Carlo Simulation of Filling High-Aspect-Ratio through Silicon Via - III
Y. Kaneko, Y. Fukiage, A. Morita (Kyoto University), T. Hayashi, K. Kondo (Osaka Prefecture University), K. Ohara, and F. Asa (C. Uyemura & Co., Ltd.)
09:00
1686
Plating through Hole with High Throwing Power Using Dual Levelers
C. F. Hsu, W. P. Dow (National Chung Hsing University), and S. M. Huang (Army Academy)
09:20
1687
Through Silicon via Filling by Electroplating Using Reduced Graphene Oxide (rGO) as a Conducting Layer
S. C. Chang and W. P. Dow (National Chung Hsing University)
09:40
Break
10:00
1688
Through-Silicon-Via(TSV) Filling by Electrochemical Deposition with Pulse-Reverse Current
S. Jin (Hanyang Univ.) and B. Yoo (Hanyang University)
10:20
1689
Cryoetching of Silicon and Advanced Materials for 3D Interconnects
R. Dussart, T. Tillocher, N. Gosset, P. Lefaucheux, R. L'jazouli (GREMI CNRS-Université d'Orléans), M. Boufnichel (STMicroelectronics), L. Zhang, J. F. de Marneffe, M. Baklanov (IMEC), E. Nishimura, K. Yatsuda, and K. Maekawa (Tokyo Electron)
11:00
1690
Electrografted Copper Seed Layer for High Aspect Ratio TSVs Interposer Metallization
F. Gaillard, T. Mourier, L. Vandroux (CEA-Leti, Minatec Campus), L. Religieux, D. Suhr, F. Raynal, and V. Mevellec (Alchimer SA)
11:20
1691
Electroless Plating for Seed Layer Deposition and Direct Metallization of Glass for Interposer Fabrication
C. Cordonier, K. Okabe, and H. Honma (Kanto Gakuin University, Materials & Surface Engineering Research Institute)
12:00
1692
Low-Cost MEMS Packaging Using Sacrificial Polymer-Based In-Situ Airgap Creation
E. Uzunlar, O. Philips, Z. Zhu, and P. A. Kohl (Georgia Institute of Technology)
12:20
1693
Advances in Wafer Bonding for 3D Integration and Other Applications
J. J. Q. Lu (Rensselaer Polytechnic Institute)
See more of: P5: Processing Materials of 3D Interconnects, Damascene, and Electronics Packaging 6
See more of: Electronic Materials and Processing
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