Through Silicon Via II

Tuesday, 7 October 2014: 08:00-12:40
Expo Center, 1st Floor, Universal 13 (Moon Palace Resort)
Shoso Shingubara and Mitsumasa Koyanagi
Recent Progress in Cu Electrodeposition for TSV (Through Silicon Via)
J. J. Kim, M. J. Kim, S. Choe, K. H. Kim, H. C. Kim, and A. Lee (Seoul National University)
Kinetic Monte Carlo Simulation of Filling High-Aspect-Ratio through Silicon Via - III
Y. Kaneko, Y. Fukiage, A. Morita (Kyoto University), T. Hayashi, K. Kondo (Osaka Prefecture University), K. Ohara, and F. Asa (C. Uyemura & Co., Ltd.)
Plating through Hole with High Throwing Power Using Dual Levelers
C. F. Hsu, W. P. Dow (National Chung Hsing University), and S. M. Huang (Army Academy)
Cryoetching of Silicon and Advanced Materials for 3D Interconnects
R. Dussart, T. Tillocher, N. Gosset, P. Lefaucheux, R. L'jazouli (GREMI CNRS-Université d'Orléans), M. Boufnichel (STMicroelectronics), L. Zhang, J. F. de Marneffe, M. Baklanov (IMEC), E. Nishimura, K. Yatsuda, and K. Maekawa (Tokyo Electron)
Electrografted Copper Seed Layer for High Aspect Ratio TSVs Interposer Metallization
F. Gaillard, T. Mourier, L. Vandroux (CEA-Leti, Minatec Campus), L. Religieux, D. Suhr, F. Raynal, and V. Mevellec (Alchimer SA)
Electroless Plating for Seed Layer Deposition and Direct Metallization of Glass for Interposer Fabrication
C. Cordonier, K. Okabe, and H. Honma (Kanto Gakuin University, Materials & Surface Engineering Research Institute)
Low-Cost MEMS Packaging Using Sacrificial Polymer-Based In-Situ Airgap Creation
E. Uzunlar, O. Philips, Z. Zhu, and P. A. Kohl (Georgia Institute of Technology)
Advances in Wafer Bonding for 3D Integration and Other Applications
J. J. Q. Lu (Rensselaer Polytechnic Institute)