(Invited) Strained SiGe on Insulator FinFETs: a P-FET Candidate for 10nm Node

Wednesday, 8 October 2014: 10:25
Expo Center, 1st Floor, Universal 8 (Moon Palace Resort)
P. Hashemi, K. Balakrishnan, A. Majumdar, S. Engelmann, M. Hopstaken, W. Kim, J. A. Ott, E. Leobandung, and D. G. Park (IBM T.J. Watson Research Center)
Performance enhancement using conventional stress elements such as stress liners or embedded source/drain is significantly decreased at extremely tight gate pitch, required for 10nm node and beyond [1]. This issue is more pronounced for non-planar architectures such as FinFETs, especially those made on SOI substrates. For p-type MOSFETs, SiGe is a great candidate due to its intrinsic lower effective mass and better transport properties than Si. SiGe has been utilized in CMOS industry for IBM SOI 32nm and 22nm generations, as a knob to adjust the PFET threshold voltage and performance enhancement [2, 3]. However, it is shown that SiGe with moderate Ge content and no strain does not provide noticeable short-channel benefit over Si and as a result, strain plays a significant role in high-performance SiGe channel pFETs [4]. While higher Ge content SiGe materials can offer lower effective mass and have potential for better transport properties [5], their reduced bandgap by increasing Ge content brings concern for some CMOS applications. This results in increased gate-induced drain leakage and high off current due to increased band-to-band or trap-assisted tunneling [6]. Moreover, the interface passivation for higher Ge content SiGe is extremely challenging resulting in significant sub-threshold leakage and degraded low field mobility. The direct consequence is the degraded short channel on-state current at the target off-current at a scaled VDD. It has been shown that by patterning of biaxially strained SiGe layers, strain can be transformed to asymmetric strain [7, 8] where the effective mass is significantly lowered and higher hole velocities can be achieved [5].  Therefore, the strain state in a scaled fin fabricated from biaxially strained substrates is pure uniaxial with optimal benefit for hole transport. The combination of uniaxial strain with great electrostatic integrity due to the non-planar device architecture as well as more manufacturing-friendly process, makes the moderate Ge content (such x=0.2-0.3) SiGe a very promising candidate for future generation of FinFETs. 

In order to evaluate the performance of s-SiGe FinFETs, SGOI substrates were fabricated using Ge condensation technique. This process is SOI CMOS compatible, where SiGe can be locally condensed in the pFET region while Si can be used for nFET or other on-chip applications. A final Ge fraction of x = 27.5% was measured by XRD, with minimal strain relaxation consistent with SIMS results (Figure 1(a)). The defectivity of SGOI substrates was measured using ex-situ Si capping followed by SECCO etch and dislocation density of ~ 1e4 cm-2 was measured for an optimized epitaxy and Ge condensation process.  A gate first process flow was developed to fabricate our SiGe pMOS FinFETs [9]. As s-SiGe reactive-ion-etch resistance is much less than that of Si, the spacer RIE process was optimized to minimize fin recess in S/D regions and thus minimize stress relaxation. Raised S/D regions were formed using an ion-implant-free process by in-situ Boron-doped (ISBD) Si1-yGe(y > 40%) epitaxy with high Boron concentration, and dopant drive-in under the spacer to form the extensions. SGOI fins with vertical sidewalls and widths as scaled as 10nm demonstrated. Figure 1(b) shows typical XTEM of s-SiGe PMOS FinFET with sub-20nm physical gate length.

Typical transfer and output characteristics of single-fin SiGe-channel PFETs (Fig. 2) exhibit excellent electrostatics with DIBL~50mV/V and SS ~90 mV/decade. In spite of high REXT ~ 0.4kΩ.μm, ION = 1.1 mA/µm was obtained at IOFF = 100 nA/µm and VDD = 1V. This high on current is attributed to the high source injection velocity exceeding 1e7 cm/s which is higher than SOI FinFETs with no stressors [10], and also higher than state-of the art bulk FinFETs [11]. Moreover, the SiGe PMOS FinFETs offers low off-state leakage suitable for high-performance and low-power applications. These criteria are hard to meet using state of the art Ge pFETs due to the significantly smaller bandgap [12]. In addition, unlike state of the art Ge pFETs, using a metal gate with a mid-gap work-function, target Vth has been achieved. In conclusion, we have demonstrated that s-SiGe channel FinFETs are a promising pFET candidate for future generations of high-performance devices and have a more manufacturable friendly process, than high-Ge content SiGe or Ge.


[1] W. Haensch, IBM J. Res. & Dev., 2006. [2] S. Krishnan, IEDM 2011. [3] C. Ortolland, IEDM 2013. [4] A. Khakifirooz, IEEE TED 2009. [5] L. Gomez, IEEE TED, 2009. [6] C. Ni Chleirigh, IEEE TED, 2008. [7] T. Irisawa, IEDM 2005. [8] P. Hashemi, APL 2007. [9] P. Hashemi, VLSI 2013. [10] T. Yamashita, VLSI 2011. [11] C. Auth, VLSI 2012. [12] B. Duriez, IEDM 2013.