Joint FET and Strain 2: Tunnel FETs and Strained Bulk and SOI "Finned" FETs

Wednesday, 8 October 2014: 10:25-12:05
Expo Center, 1st Floor, Universal 8 (Moon Palace Resort)
Atsushi Ogura and Y. Yee Chia
(Invited) Strained SiGe on Insulator FinFETs: a P-FET Candidate for 10nm Node
P. Hashemi, K. Balakrishnan, A. Majumdar, S. Engelmann, M. Hopstaken, W. Kim, J. A. Ott, E. Leobandung, and D. G. Park (IBM T.J. Watson Research Center)
Atomistic Modeling of Strained SiGe Nanofins
S. T. Dunham, H. Lai, and R. Chen (University of Washington)
SOI and Bulk FinFET Alternatives from the Perspective of Strain Engineering
I. V. Peidous, C. Lottes, and C. Jost (SunEdison Semiconductor, Ltd.)
(Invited) Challenges and Opportunities in the Design of Tunnel FETs: Materials, Device Architectures, and Defects
D. Esseni (University of Udine), M. G. Pala (IMEP-LAHC, Grenoble-INP), A. Revelant, P. Palestri, L. Selmi (University of Udine), M. Li, G. Snider, D. Jena, and H. G. Xing (University of Notre Dame)