(Invited) Challenges and Opportunities in the Design of Tunnel FETs: Materials, Device Architectures, and Defects

Wednesday, 8 October 2014: 11:35
Expo Center, 1st Floor, Universal 8 (Moon Palace Resort)
D. Esseni (University of Udine), M. G. Pala (IMEP-LAHC, Grenoble-INP), A. Revelant, P. Palestri, L. Selmi (University of Udine), M. Li, G. Snider, D. Jena, and H. G. Xing (University of Notre Dame)
Most of the digital systems around us today are power limited, and their performance is essentially the best that it can be obtained with the available power or energy budget. The scaling of the supply voltage is the most effective measure to improve the energy efficiency of CMOS circuits, however the degradation of dynamic performance with decreasing VDD is today particularly challenging, and practically limits further VDD reduction. A better tradeoff between dynamic performance and standby power may be achieved thanks to small slope switches (i.e. transistors having a sub-threshold swing, SS, better than 60mV/dec at room temperature), and the ITRS has singled out Tunnel FETs as the most promising small SS devices.

In this framework, I will then briefly introduce the working principles of Tunnel FETs and emphasize how the choice of the material systems plays a crucial role in the overall design of the devices. I will then discuss examples of challenges and opportunities in the design of Tunnel FETs, touching strain engineering, hetero-junctions, size induced quantization effects, interface defects related design issues and variability. I will also introduce, time permitting, some very recent developments in the field, which try to exploit transition metal dichalcogenides (TMD) MX2 (M = Mo, W and X = S, Se), which form a family of quasi-2D crystals having an energy band-gap ranging between 1eV to 2eV, to design vertical tunnel based transistors.