SOI and Bulk FinFET Alternatives from the Perspective of Strain Engineering

Wednesday, 8 October 2014: 11:15
Expo Center, 1st Floor, Universal 8 (Moon Palace Resort)
I. V. Peidous, C. Lottes, and C. Jost (SunEdison Semiconductor, Ltd.)
Fabrication of MOSFETs with mechanically strained channels has been an effective means for enhancing transistor drive currents and improving performance of CMOS circuits. FinFET devices appear to suit best for leading-edge ULSI and may be scaled to satisfy the requirements of 10 nm technology generations and beyond. There are two generic options for FinFET implementation – SOI and Bulk. The effectiveness of FinFET strain engineering is one of the decisive factors for selecting a preferred FinFET option.

The purpose of the present work is to provide an insight into the stress states of strain-engineered SOI and Bulk FinFETs. The results of computer simulations quantifying the stress effects on carrier mobility in FinFETs of different geometries and channel orientations are presented. The modeling was performed using a specially developed 2D FEM algorithm that enabled fast turnaround in conducting numerous iterative simulation experiments.

The obtained results show that embedded SiGe stressors (eSiGe) formed in Source/Drain areas of FinFETs are the key element for enhancing drive currents of PFETs to the level comparable with NFETs. However, due to the differences in transistor architectures, the stress induced by eSiGe in SOI FinFET channels and the corresponding change of the carrier mobility is about 2 times lower than that in bulk FinFETs. On the other hand, SOI offers a higher degree of freedom for stress engineering to compensate eSiGe deficiency. SOI FinFET designers may consider alternative crystal orientations for Fins, strained SOI, and low-defect Ge or III-V semiconductors on insulator.