Modeling and Integration Phenomena of metal-metal direct bonding technology

 

Metal layer bonding is nowadays at the center of the latest wafer bonding researches. This technology enables innovative architectures in 3D, LED’s, MeM’s and Power devices. Unlike other metal bonding techniques, the non-thermo compression metal-metal direct bonding is performed at room temperature under atmospheric pressure ensuring minimal distortion and stress on the bonded wafers [1-3].

We have already published bonding results for copper, titanium and tungsten layers. As a summary the bonding behavior and so the bonding energy is mainly monitored by the presence of grain boundaries and the metal oxide layer at the metal surface. Smart Cut^TMwas also achieved with these three types of bonding [4].

We have now developed a physical chemical model approach to explain the evolution of the bonding energy and the interface structure with regards of the metal bonding integration and kinetics phenomena. We have shown that at room temperature the bonding energy is driven by the nature of the metallic oxide at the surface and the chemical reaction between the metal and the oxygen. With temperature the oxygen diffusion coefficient enhanced by the grain boundaries paths is the main key parameter, fig.1 [5].

Other integration parameters are of importance. One of them is the barrier layer (presence or nature) under the metal layer. Switching from TiN to TaN layers the bonding energy was increased by a factor of more than 2. fig.2. This was explained by the absence of void segregation during annealing at the weak TiN/ Cu interface. The same result was obtained by inserting a Ti layer between the TiN and the copper. On the other hand for copper layers of 5µm it was impossible to debond the wafers at room temperature due to the increase size of the grains.

The model will be explained and detailed with extensive characterization experiments such as TEM, slice 3D SEM and picosecond analysis. Integration of metal bonding in devices and bonding energy measurement will be also discussed.

Acknowledgment:

                The authors would like to thank the French government for its financial support under the convention OI 1262-67155, Connect 3D; SOITEC for its financial support, especially I Radu, and G Gaudin for fruitful discussions. Thanks also to Maurice Rivoire and Daniel Scevola for surface preparation and G Audoit, B Florin and Hugo Danzas for TEM sample preparation.

References:

[1]I. Radu, G. Gaudin, W. Van Den Daele et al “Novel Low Temperature 3D Wafer Stacking Technology for High Density Device Integration”In proceeding of: IEE ESSDERC/ 2013

[2] M. Sadaka , L. Di Cioccio et al., “Building Blocks For Wafer Level 3D Integration”, Solid State Technology, 52 (2009) p.20.

[3] L.  Di Cioccio, P. Gueguen, R. Taibi.et al , “An Overview of Patterned Metal /Dielectric Surface Bonding: Mechanism, Alignment and Characterization”, JECS, Volume: 158   Issue: 6   Pages: P81-P86   Published: 2011

[4] L. Di Cioccio,  I. Radu, F. Baudin et al. « Wafer Level 3D Stacking using Smart Cut^TM and Metal-Metal Direct Bonding Technology”Proceeding of the PRIME 2012 Conference Hawai [5] M.Martinez, M.Legros,T. Signamarcheix, et al “Mechanisms of copper direct bonding observed by in-situ and quantitative transmission electron microscopy” THIN SOLID FILMS, Volume: 530,Pages: 96-99 2013