Etch Challenges for 3D NAND Flash Technology

Tuesday, 7 October 2014: 15:20
Expo Center, 1st Floor, Universal 5 (Moon Palace Resort)
A. H. Khan, S. Srinivasan, J. Choi, A. Athayde, and R. Achutharaman (Applied Materials)
Current 2D NAND scaling is approaching technology limitation in both lithography and device performance arena.  To address the lithography challenges at the 1x nodes and the well-known scaling issues associated with planar NAND, 3D flash technology is being developed and is expected to greatly reduce the lithography burden albeit shifting it to deposition and etch.  The emerging 3D flash architecture requires depositing alternating layer stacks and then etching those stacked layers with extreme precision.  Staircase etch for contact landing, hard mask etch, gate trench etch, channel hole etch and staircase contact etch are the main critical etches required to manufacture 3D flash device (Figure 1). 

Plasma etching processes involved in the fabrication of 3D flash devices are becoming increasingly challenging.  The staircase etch, which requires lateral resist mask etch followed by vertical stacked layer etch, repeated in multiple the lateral/vertical etch cycles, to form staircase shaped contact landing pads, offers unique challenges in lateral to vertical etch rate control of resist mask, resist mask shape control, selectivity control of the stacked layer etch, staircase step width control and step width uniformity control.  Hardmask open, gate trench etch, channel hole etch, and staircase contact etch create significant challenges for etching, especially of high aspect ratio (HAR) features ranging in aspect ratio from 30:1 to >80:1.  Furthermore, etching through the HAR alternating layer stacks intensifies the demands on the etch process, which must be capable of etching distortion free, vertical profiles free of bending, faceting and feature clogging.  Additionally, smooth sidewall transitions in the alternating stack, and very high selectivity to the tiny pad are required, especially for the staircase contact etch application, which combines extreme simultaneous multi-level etch at aspect ratios ranging from 30:1 to >80:1 along with extremely high selectivity for negligible loss of the underlying contacted material.

In this paper we will present etch hardware and process development solutions provided to overcome these difficult etch challenges for staircase etch, hard mask open, gate trench etch, channel hole etch, and staircase contact etch applications to enable 3D NAND flash technology.