Ge FET Fabrication by Plasma Etch at 45nm Pitch

The effect of germanium channel introduction  was shown [1] to be sizable up to the high performance expectations when technological nodes pass 10-nm line. At that moment, the Si-based fin FET (FFT) technology should approach its limits, which would not be feasible to overcome by applying any boosting techniques anymore.

In the work, a self-aligned double patterning (SADP) was selected to print the Ge fins with 45-nm pitch (from initial 90-nm), but in the future the EUV litho is considered to become an ultimate way to pattern active layer structures for such small nodes.  The dry plasma etch development was performed in the Lam Research 2300® Kiyo®E Series 300 mm conductor etch reactor. The SiCl₄-based advanced chamber condition control strategy was applied prior to etching of every individual wafer, which helps provide superior etch reproducibility [2].

The 30-nm Ge channel was epitaxially grown on top of a thick SiGe strain-relaxed buffer (SRB) layer. The targeted depth of fin etch was set to be in the range of 120-140 nm, which means the etching should be done through the Ge channel stopping in the SiGe SRB. The final clean of the structure was performed ex situ to strip polymers formed during the Ge and SiGe etching, which was done with N₂O/forming gas plasmas followed by a short 0.6%HF clean [3].

Fig.1. shows the patterning stack used for SADP of Ge/SiGe fins. The critical dimensions (CDs) obtained during the first transfer layer etching (called CORE etch) determine the space between fins in the final 45-nm pitch structure, while the thickness of SiN spacer deposited on top of the CORE determines the final fin’s CD. More details on SADP sequence can be found in [4].

After both the CORE and the SiN spacer patterning were completed, the focus of the study was to develop a Ge/SiGe fin etch process using the second transfer layer as a mask. A slightly tapered single-sloped fin profile is the desired outcome of such patterning, which structure has to be compatible with the following step of void-free oxide filling.

Fig.2 depicts two types of the Ge/SiGe FFT etching. The result of the fin etching with the main etch chemistry consisting of HBr/Cl₂/O₂ and CH₂F₂ can be seen in Fig.2a. The process conditions were taken from the study of 200-nm relaxed pitch Ge FFT patterning [5], where the CH₂F₂–based passivation used during fin etch was shown to allow for an advanced controlling of the fin shape. However, the mechanism does not work so well for 45-nm dense pitch structures where the diffusion of active species into the narrow trenches is limited. It leads to several issues. First, there is a pronounced depth loading, which means the depth difference between isolated and dense structures. Thus, for the 95-nm tall fins shown in Fig.2a, the isolated structures were etched almost twice as deep.

Re-entered profile in the top part of a fin is another problem of the structure shown in Fig. 2a, though the latter could probably be fixed by means of process optimization similarly to what was done in the etch of Fig. 2b.

As it was shown for Si, depth loading can be naturally addressed by switching to a Cl₂-based chemistry without any fluorocarbon or hydrocarbon additives [6].  Thus, an alternating process consisting of a Cl₂-based etching step and O₂-based passivation has been successfully tested to pattern the Ge/SiGe fins, shown in Fig. 2b. In the etching step of such cyclic process, the RF bias pulsing was applied at 100Hz in order to facilitate the etch process selectivity. More information on RF pulsing advantages can be found in [7].