Alternative to H3PO4 for Si3N4 removal by using chemical downstream etching

Si₃N₄ is widely used in the semiconductor industry as a sacrificial etch stop layer, implantation spacers, hard mask for selective epitaxy. Si₃N₄ is resistant to many RIE process, to fluoridric acid, and can be easily removed thanks to hot phosphoric acid with excellent selectivity to other materials (Si and SiO₂). However hot phosphoric process presents majors drawbacks: Done in wet benches, the levels of metallic and particular contamination, process uniformity, do not match all the requirements of 14nm node and beyond. Surface preparation standards indeed converge towards single wafer cleans for these reasons. But typical etch rate with hot phosphoric are too low (>1Å/min) to be compatible with a single wafer approach.

Plasma removal is a possible alternative, either by RIE or CDE (Chemical Downstream Etching). If the selectivity to the SiO₂is usually very low for RIE (~15), selectivity for CDE reactors up to 60 have been reported in the last years, increasing the interest for this technique.

In the present work we evaluated the etching selectivity of a new CDE process. We achieved successfully its integration in replacement of hot phosphoric acid for a process step denoted as nitride pull back (NPB): In VLSI circuits, transistors are electrically insulated by trenches filled with SiO₂. As the filling is done by conformal deposition methods, it is greatly facilitated by an etch back of the top Si₃N₄ (fig.1). One problem in this case is that CDE used here could etch the silicon in the trench very quickly: this disadvantage has been overcome by oxidizing the flanks of the trench with a RTP process. In this configuration, a SiO₂ liner is formed at the surface of the trench. However RTP process is known to create also an oxidized layer at the surface of the Si₃N₄ that can delay the etching.

In this context we evaluated the selectivity of the process on full sheet layers. For that purpose we generated SiN layers made by LPCVD furnace at 770°C, and thermal SIO₂ made by RTP. Top of the Si₃N₄layers were also oxidized to evaluate the etching delay induced by this surface oxidation.

Fig2. reports the Si₃N₄ and SiO₂ etch rates vs. etching time. Si₃N₄ removal rate is very stable around 150 Å/min. In the same time SiO₂ etch rate increases moderately form 0.6 to 1.6 Å/min. As a result, the average selectivity is always higher than 100:1 and reaches 250:1 at the early stage of the process. If oxidized, an etch delay is induced and Si₃N₄ etch rates and selectivity to SIO₂ drops rapidly with the oxidation budget (fig.3): Thus a moderate oxidation has been done on the patterned wafer to preserve both Si₃N₄ etch rate and the liner integrity. Thickness measurements returned a Si₃N₄ removal of 120Å with a good within wafer uniformity (3.5%), and a negligible SIO₂ removal (<0.1Å). TEM cross sections (Fig.4) confirmed that the oxide liner and underlying silicon are preserved during the Si₃N₄ etching.

Differences of etch rates between dense and isolated areas have been evaluated as far as the defectivity aspects and will be discussed in the full paper.