Delamination Root Cause in Temporary Bonding

Tuesday, 7 October 2014: 10:00
Expo Center, 1st Floor, Universal 9 (Moon Palace Resort)
K. Vial (EV Group), F. Fournel (CEA, Leti, Minatec Campus), M. Wimplinger, J. Burggraf, J. Bravin (EV Group), P. Montméat, and M. Pellat (CEA, Leti, Minatec Campus)
In the past few years, the More than Moore initiative has led to a focus on developing new process flows in the 3D-IC field [1-2]. One of the key points for an entire 3D integration success is being able to handle the thin wafer during backside processing reliably. Temporary bonding has emerged as one of the answers [3-4]. However, some challenges still need to be overcome in order to fully control and understand this technique.

Temporary bonding is based on the use of a carrier wafer bonded to a device wafer, thanks to an adhesive layer. Depending on the temporary bonding technology used, an additional release layer or anti-sticking-layer may be added to the stack to facilitate debonding. For any technology, the temporarily bonded stack consisting of the device and the carrier wafer has to withstand the backside process flow while being easily de-bondable at the end of this process.

In order to fulfill these requirements, the temporary adhesive is playing a major role: it has to demonstrate at the same time high thermal resistance (above 260°C for 30min), as well as an excellent cleanability or removability after simple de-bonding. The adhesive must also provide a means for embedding the front side topology of the device wafer while demonstrating resistance against process chemicals and exhibiting compatibility with processes requiring vacuum environments. All these criteria are difficult to match with one solution because they require different polymer properties. Thermoplastic, silicone based and polyimide based materials as well as other polymers have been investigated with respect to overcoming those challenges [5-6-7].

Specifically, the delamination defect observed - most commonly with thermoplastic solutions- is an important issue remaining not fully understood. This paper aims at studying the root cause of delamination defects observed in temporary bonding, and defines which key parameters of the device or of the 3D integration process itself should be checked before selecting the temporary bonding material. Based on that, process windows for existing and new materials could be then studied regarding the key parameters defined through this work.

To start, parameters which could be the possible root cause for delamination have been defined. This delamination phenomenon is occurring frequently during PECVD deposition. This deposition process is done under temperature and vacuum. Moreover, the use of plasma is creating a local increase of the temperature of the wafer. The thin device can also react to the deposition, by changing its stress or its bow during the process. Five factors are then discriminated from these observations as possible root cause (process temperature, vacuum level, thermal gradient, bow and warp, intrinsic stress). Simple test vehicles have been developed to study individually each of the five parameters listed above. At the end, some tests combining different parameters have finally shown the complex mechanism behind the delamination phenomenon.

In this paper, we will present each test vehicle, the respective results and observations. At the end we will see that the combination of three parameters is leading to the delamination defect and the interaction between them will be discussed. Moreover mechanical simulation will be carried out to define numerical criteria for describing and finally avoiding such delaminations.


[1] J. U. Knickernocker et al., “2.5D and 3D technology Challenges and Test Vehicle Demonstrations”, Proc. of Electronic Components and Technology Conference, 2012, pp.1068-1076.

[2] S. Cheramy et Al., “200mm & 300mm processes & characterization for face to back flow chart for WideI/O”, Proc. of International Microelectronics And Packaging Society, 2012, pp. 8-13

[3] J. Burggraf et al., “Low temperature wafer bonding for 3D applications”, Proc. of WaferBond Conference, 2013, pp. 127-128

[4] T. Matthias et al., “Room temperature debonding – an enabling technology for TSV and 3D integration”, Proc. of Electronic Packaging and Technology Conference, 2012, pp. 244-247

[5] A. Jouve et al., “WSS and ZoneBONDTMtemporary bonding techniques comparison for 80µm and 55µm functional interposer creation”, Proc. of Electronic Components and Technology Conference, 2013, pp. 101-106

[6] K. Vial et al., “Challenges and solutions for ultra-thin (50µm) silicon using innovative ZoneBONDTMprocess”, Proc. of Electronic Packaging and Technology Conference, 2012, pp. 450-455

[7] P. Montméat et al., “TTV value improvement of thin films obtained by temporary bonding ZoneBONDTM  technology”, Proc. of WaferBond Conference, 2013, pp. 147-148