Characterization of Epitaxial Si:C:P and Si:P Layers for Source/Drain Formation in Advanced Bulk FinFETs

Since quite a few years, source/drain strain engineering has been widely adopted in the manufacturing of integrated circuits to increase the carrier mobility and drive current of Si MOSFETs [1-3]. Even for sub 20nm bulk-FinFET devices, the source/drain epitaxy is expected to remain an effective and essential ingredient for device performance improvement [4,5]. In this work, we present the characterization of epitaxial in-situ phosphorus doped silicon and silicon carbon films (Si:P/Si:C:P) and discuss their integration in a raised and recessed bulk-fin geometry. The Si:C:P layers have been deposited using a low temperature selective Cyclic Deposition and Etch (CDE) process [6,7] while the Si:P films were grown using both cyclic and non-cyclic selective processes. All depositions were done in a 300 mm ASM Intrepid XP^TM reduced-pressure chemical vapor deposition system (RPCVD) using traditional deposition and etch precursors. For the CDE processes discussed in this work, typical phosphorus concentrations of ~3e20 at/cm³ were obtained for carbon contents ranging from 0 to 2%. Fig.1 shows the resistivity of such layers versus total carbon content derived from micro-Hall and Secondary Ion Mass Spectrometry (SIMS) measurements on (80µm)² pads. Introducing more carbon in the layers leads to an expected increase in resistivity due to a loss in substitutional phosphorus [8]. For the wafers with full gate and spacers, the epi was grown on underlying activated extensions without recess.  Also shown is the resistivity decrease by use of bilayers with equal Si:C:P/Si:P thicknesses. For the non-CDE Si:P processes, phosphorus contents as high as 10% could be achieved which introduce tensile strain without the presence of carbon [9]. To be compatible with scaled fin dimensions, the in-situ H₂ bake conditions were optimized to minimize the Si reflow and still preserve a sufficiently large oxide removal efficiency in combination with the pre-epi HF dip. Examples of reflow during H₂ bake are shown in Fig.2.The selectivity of the epi processes was tuned by varying the amount of etching per cycle by either changing the etch process parameters or the etch time per cycle. Increasing the etching per cycle makes the process selective towards the oxide and nitride layers used in the integrated devices and also decreases the side-wall roughness along the fins. An optimum has to be found as the increased etching also lowers the carbon content and reduces the process throughput. Finally, we also report on the use of post-epi millisecond laser anneal which turns out to be a useful integration knob to lower the post epi resistivity while still preserving the strain. The largest improvements can be observed for strained Si:P layers with high phosphorus incorporation. From Hall and SIMS measurements on blanket and patterned wafers it can be derived that the dopant activation is strongly increased (in some cases up to 300%) resulting in a ~50% reduction of the resistivity which makes this process an attractive alternative to conventional carbon doped layers (example see Fig.3).

Acknowledgements

The imec core CMOS program members, European commission, local authorities and imec pilot line are acknowledged for their support.  

References

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