(Invited) Fabrication of Pure-GaB Ge-on-Si Photodiodes for Well-Controlled 100-pA-Level Dark Currents

Thursday, 9 October 2014: 09:10
Expo Center, 1st Floor, Universal 11 (Moon Palace Resort)
A. Sammak (TUDelft), M. Aminian (EPFL), L. Qi, W. B. de Boer (TUDelft), E. Charbon (EPFL, TUDelft), and L. K. Nanver (TUDelft)
In this paper the influence of PureGaB Ge-on-Si photodiode (PD) design strategies that aim to reduce local loading effects during Ge deposition are presented. As compared to  our earlier devices, the elimination of parasitic Ge and concomitant As-doping deposition from oxide regions surrounding the deposition windows also leads to an improved diode ideality. For micrometer-sized diodes, ideality factors of less than 1.1 and dark currents in the range of 100 pA are now achieved, which to our knowledge are by far the lowest values reported in the literature. Moreover, improvements in the flatness of the Ge-island surface facilitated a process flow for contacting the diode perimeter while leaving a large oxide-covered PureGaB-only light entrance window on the central photosensitive region.

In Fig.1 the basic process flow is illustrated for fabricating the improved PureGaB Ge PDs. First a 1-µm-thick SiO2 layer is deposited and patterned on the Si surface. In contrast to earlier flows, the windows destined to be filled with Ge for PD realization are surrounded by another ring-shaped window where Ge also is deposited. After this patterning, the wafers are loaded into a CVD reactor and in one deposition cycle the n-type Ge and nm-thin Ga/B layer-stack (PureGaB) is grown. It was found that a 5-µm-thick ring was sufficient to absorb most of the Ge and As atoms that otherwise would reach the main PD window by lateral diffusion across the SiO2 as a local loading effect. After Ge deposition, the wafers are transferred to a PECVD reactor for deposition of a second SiO2layer which is subsequently patterned and etched with a soft-landing to give access to the perimeter regions of the Ge-PDs. Then the metallization is sputtered on both sides of the wafer to give access to the anode and cathode of the Ge-PDs. Finally the front-side metal is patterned and removed from the center of the Ge-PDs.

Top-view SEM images of the fabricated PureGaB Ge PD before and after the metal removal, are shown in Fig.2.a and Fig.2.b, respectively. It is shown that this extra metal removal step on the surface of the Ge-PD, creates a clean oxide-covered PureGaB-only front-entrance window with no indication of  damage to PureGaB surface.

The diode quality was checked by I-V measurements of PureGaB Ge-PDs with various sizes. In Fig.3 the I-V curves are shown for 3 different sizes. An area/perimeter analysis reveals that the current is area-dependent which means that the perimeter leakage that usually is present in Ge diodes is eliminated in the PureGaB PD’s. The exact reason for this behavior is yet unknown since several factors are counteracting each other. Effects that may play a role are: the Ge does not attach to the sidewalls of the SiO2window; the PureGaB deposition is conformal over the Ge surface; the depletion and associated electric field at the perimeter are modified by the presence of the oxide and any increase of the As-doping at the perimeter due to the local loading effect.   

The n-doping of the Ge-islands is determined by Capacitance-Voltage (C-V) profiling, some results of which are shown in Fig.4. From the almost perfect area-dependent behavior of the I-V characteristics it is expected that the n-doping is similar in all cases.  In fact the doping goes from about 3×1015 cm-3 to 1016 cm-3 when going from a PD area of 26×26 µm2 to 11×11 µm2. This increase in doping with PD area can possibly be accorded to an increasing, but small, local loading effect due to an increase in oxide area around the smaller devices. This is layout dependent and can be corrected for future designs.

All in all, the suppression of local loading effects significantly improves the electrical diode characteristics and also the yield: an almost 100% yield has been achieved for arrays of 300×1 PDs of varying sizes.