A Novel Approach to Isolating the Edge of the Shallow Trench Isolation in SiGe HBTs for Improved Device Performance

Monday, 6 October 2014: 14:40
Expo Center, 1st Floor, Universal 8 (Moon Palace Resort)
R. A. Camillo-Castillo, Q. Z. Liu, V. Jain, J. W. Adkisson (IBM Microelectronics Division), M. H. Khater (IBM T.J. Watson Research Center), P. Gray, J. J. Pekarik, R. Malladi, and D. L. Harame (IBM Microelectronics Division)
Scaling silicon germanium heterojunction bipolar transistors (SiGe HBTs) to attain simultaneous increases in the figures of merit, fT and fMAX has necessitated a deep understanding of the inherent features of the process as it relates to the final device performance. The faceted nature of the base epitaxial growth on the periphery of the shallow trench isolation has been the focus of several investigations which have demonstrated the role it plays in the extrinsic collector-base capacitance. In this work, a novel approach to isolating the device periphery is presented in which a field polysilicon protect layer is used to isolate the edge of the active silicon region in the vicinity where the faceted growth typically occurs, for a 300/350 fT/fMAX SiGe HBT NPN. Layout variations in the location of the field polysilicon layer relative to the edge of the active silicon region, results in marked changes in the intrinsic device, with increases in fT/fMAX of 15/20GHz respectively. Technology computer-aided device techniques are utilized to understand the process and device changes driving the improvements in device performance observed and will be discussed.