(Invited) Reliability of SiGe HBTs in Long-Term Operation

Monday, 6 October 2014: 14:10
Expo Center, 1st Floor, Universal 8 (Moon Palace Resort)
G. G. Fischer (IHP)

            In the ongoing development towards RF circuits with still higher operation frequencies SiGe HBT technologies continuously have to prove their competitiveness against advanced Si CMOS and compound semiconductor millimeter-wave circuits. Yet, besides excellent RF performance at circuit operation frequencies – meanwhile even well beyond 100 GHz –customer focus is also put on operating constraints (“safe operating area”, SOA) and long-term reliability of the devices.

If the HBT power load in a circuit stays within the SOA limits but collector voltage surpasses open-base breakdown voltage (BVCEO) or the emitter-base (EB) diode is reverse biased a gradual decrease of the HBT current gain (“beta ageing”) can usually be observed (Fig. 1a). This beta degradation is correlated to an increase of the base recombination current caused by recombination centers (“traps”) at dielectric interfaces. These again are being created by hot carrier injection (“HCI”).

This interface trap generation and the gradual character of ageing are in contrast with device failure of III-V devices where defects are generated inside the semiconductor and failure shows more abrupt and end-of-life characteristics [1].

Concerning HBT reliability the questions to address then are: What is the maximum HBT beta degradation tolerable for any specific circuit operation? Will it stay within this limit during the anticipated circuit life-time (up to 20 years for space applications)? Our intention therefore was to develop an ageing function which describes base current change or beta degradation, respectively, as function of electrical stressors, ambient temperature, and stress time. The experimental setups to evaluate ageing are forward and reverse bias stress conditions which we applied for up to 1000h and in a temperature range from -40°C up to 150°C.

Operation Constraints

The SOA to which device operation should be restricted can be derived from the common-base output characteristics which indicate device instabilities by current pinch-in or electro-thermal runaway. For low-voltages electro-migration will define maximum current densities. The latter can to be avoided be defining proper design guidelines for the metal line layout.

Interface Defect Generation and Annihilation

Even within SOA sufficiently high electrical fields in the collector-base (CB) space charge region will trigger avalanche carrier multiplication there and part of them will be accelerated towards EB and CB spacer oxides interfaces (HCI). Subsequently, interface traps will be created by de-passivation of Si dangling bonds. Trap density is expected to evolve as Nit ~ tα with α ≈ 0.25 [2] as long as the reaction is far from saturation (i.e. trap density becomes comparable to the total areal density of interface dangling bonds). Contrary, thermal activated hydrogen re-passivation of traps leads to beta recovery.

Electrical Stress and Annealing Tests

Currently, two types of electrical stress tests have been established as basis for SiGe HBT reliability evaluation:

  • Forward “mixed-mode” (MM) stress with applied VCB,stress > BVCEO and forced emitter current density JE,stress up to a few times the value corresponding to peak-fT,
  • “REV” stress with reverse biased BE junction.

Additionally, to study defect annealing we applied a combination of high current and VCB,stress > BVCEO at ambient temperatures up to 150°C to achieve junction temperatures well above 200°C. Figure 1a shows as an example the impact of 100 h REV stress and subsequent anneal on a HBT with 250 GHz peak-fT from IHP’s 0.13 µm BiCMOS technology [3]. At VBE = 0.7 V over 90% beta reduction can be observed during reverse stress (2) but annealing with junction temperature reaching 300°C lead to almost complete beta recovery (3).

Ageing Function

                The additional trap recombination saturation currents have been evaluated as function of the relevant stressors [4]

IBEr,MM = f(VCB,stress, IE,stress, Tambient)·tα
IBEr,REV = f(VEB,stress, Tambient)·tα

and can be added to the according compact model base current. Figure 1b shows for example base current increase as function of VEB,stressafter 100h of REV stress. This ageing function can be used to predict HBT ageing and its impact on circuit performance during circuit life cycle.


[1] G. Freeman et al., Microelectronics Reliability, vol. 44, p. 397 (2004).

[2] K.A. Moen et al., IEEE Trans. on Electr. Dev., vol. 59(11), p. 2895 (2012).

[2] H. Rücker et al., IEEE J. Solid-State Circuits, vol. 45(9), p. 1678 (2010).

[3] G.G. Fischer et al., Proc. IEEE BCTM, p. 167 (2013).