Low Cost, Scalable and Selective Electrochemical TSV Fill Technology for 3D IC Interconnects

Physical and economical limitations for 2D scaling (so called “Moore’s Law”) prevents further increase of integration density to improve the performance of integrated circuits (IC). These challenges have stimulated the development of 3D through-silicon via (TSV) technology (so called “More than Moore”) in order to increase the speed and the bandwidth of the devices as well as to decrease the form factor and power consumption of integrated microsystems. However, the implementation of 3D TSV technology is limited by the high cost of 3D TSV fill (due to the use of expensive vapor deposition and chemical-mechanical processes) and its poor scalability (due to low conformality of physical and chemical vapor deposited films) to high TSV aspect ratios and smaller via sizes (to increase I/O). The objective of this investigation is to address the cost and scalability issues in order to enable cost-effective and reliable fill of high aspect ratio 3D TSVs. 

In this paper, we will review the low temperature and scalable process technology for 3D TSV fill employing the selective electrochemical through-via metal (Ni alloy/Cu or Co alloy/Cu) filling technology which is more economical because it will eliminate expensive chemical-mechanical polishing (CMP) process and replace expensive plasma-enhanced chemical vapor deposition (PE CVD) and physical vapor deposition (PVD) processes with low cost, lower temperature (<100 ^oC), more scalable (AR > 30:1) selective electrochemical process (LoCoSS process). LoCoSS process technology includes the following major electrochemical process steps: anodic oxidation to form isolation layer, selective electroless barrier deposition and selective electrochemical fill that can be implemented using one LoCoSS electrochemical processing tool instead of four POR processing tools utilizing different technologies – PE CVD isolation, PVD barrier/seed, Electrofill and CMP.

The activation of thin continuous electroless barrier films (Ni or Co alloys) with high adhesion on the isolation surface (SiO₂) is challenging. To overcome this technical risk, a novel nanoactivation process has been developed with the use of self-assembled monolayers [Si-(CH₂)_x-NH₂-OH] and catalytic functionalized nanoparticles (Pd/Cu). To increase the adhesion of the deposited barrier films, the covalent bonding between substrate and the SAM binding layer has been engineered through the proper choice of the functional groups. Selective activation has been achieved through the mechanical removal of catalysts from the front surface (except inside the TSV’s) and the use of photosensitive TiO₂/catalyst process. Besides, robust and defect-free fill of high aspect ratio TSV’s requires the development of electroless Cu superfill process with the use of suppressing additives in the plating solution such as high molecular weight polyacrylic acid (PAA) and polyethylene glycols (PEG). Selective electroless Cu plating into high aspect ratio TSV was successfully demonstrated with complete coverage of electroless barrier layer and low overplating on the field. Copper electroplating from NANO3D suppression-based plating solutions was also used to enable high speed and uniform plating of flat Cu bumps that can be used to interconnect chips in 3D microelectronics systems. 

LoCoSS technology could accelerate the mass-scale adoption of low cost and scalable TSV technology in semiconductor manufacturing. Implementation of our proprietary LoCoSS process will lower the cost of 3D ICs with the potential to reduce the cost by over 2X and increase scalability by over 3X for volume production. Besides, enabling low cost 3D ICs with our technology will allow heterogeneous system generation for next generation smart phones and other communication devices as well as increase of the bandwidth, memory capacity and decrease of the signal transmission delay within computing chips.