Through Silicon Via I

Monday, 6 October 2014: 13:00-16:00
Expo Center, 1st Floor, Universal 13 (Moon Palace Resort)
Chairs:
Kazuo Kondo , S. Mathad , Rohan Akolkar and Wei-Ping Dow
13:00
1678
R&D Overview of 3D Integration Technology Using TSV in Japan
M. Kada (Osaka Prefecture University)
13:40
1679
5minutes TSV Filling
C. Funaahashi, K. Kondo, M. Yokoi, N. Okamoto, and T. Saito (Osaka Prefecture University)
14:00
1680
Low Cost, Scalable and Selective Electrochemical TSV Fill Technology for 3D IC Interconnects
V. M. Dubin (NANO3D SYSTEMS LLC)
14:20
Break
14:40
1681
3D Wafer Level Heterogeneous Integration
M. J. Wolf and K. D. Lang (Fraunhofer Institute for Reliability and Microintegration IZM)
15:20
1682
A Stable Cu Nanoparticles Used for Seed Layer Deposition of through Silicon Via
Y. L. Tsai and W. P. Dow (National Chung Hsing University)
15:40
1683
Effect of Cupric Methanesulfonate on through-Hole Filling by Copper Electroplating
J. X. Ye and W. P. Dow (National Chung Hsing University)
See more of: P5: Processing Materials of 3D Interconnects, Damascene, and Electronics Packaging 6
See more of: Electronic Materials and Processing
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