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(Invited) Gate-All-Around Ge FETs
Introduction
For the technology nodes of 10 nm and beyond, the high mobility channels (Ge, and III-V) are required to enhance drive current, and new device architectures (FinFET, tri-gates [1], and GAA FETs [2]) are desired to reduce power. Since the Ge epichannel directly on Si can be a low-cost solution, Ge attracts the most interesting for emergent device integration. The misfits of the bottom Ge can be removal by anisotropic etching. The nearly defect-free Ge channel can be formed for GAA transistors.
Experiment
The intrinsic and heavily doped p-type epi-Ge layer were grown on SOI by the RTCVD for INV and JL devices, respectively. The Ge fins were patterned and formed by anisotropic etching with Cl2/HBr-based plasma to etch away the high defective Ge near Ge/Si interface. The floating Ge fin on SOI was made due to the higher etching selectivity of Ge than Si and the enhanced etching rate by the defects. After the Al2O3/GeO2 gate stack formation, the contact electrodes were deposited and defined. For INV devices, the S/D were implanted with P (1×1015, 18 keV) and activated at 550°C for 30s. For JL devices, The Nch of 5×1018 cm-3 was in-situ doped by PH3 flow.
Results and Discussions
Since the mobility of (111) Ge is 2 times than (100) Ge, the Ge fin with (111) sidewalls are fabricated to take the advantage of the sidewall enhanced mobility. The transfer characteristics of the INV Ge GAA nFETs with the Wfin of 58 nm and the Lg of 350 nm are shown in Fig. 1. Thanks to the GAA structure and the removal of the defect region, the SS of ~ 94 mV/dec and Ion/Ioff of 1.6× 104 at VDS = 0.05V is achieved. The 2x enhancement of the Ion is also observed for the Ge GAA nFET with (111) sidewalls relatively to the Ge FinFET with ~(110) sidewalls. The EOT of 5.5nm obtained from planar devices, and Dit of 1×1012cm-2eV-1 extracted from the simulation. The TEM image of Ge fin with (111) sidewall is shown in the inset of Fig. 1.
The transfer characteristics of the JL Ge GAA pFETs with the Wfin of 27 nm and the Lg of 250 nm are shown in Fig. 2. The SS of ~ 95 mV/dec and Ion/Ioff of 1.5×106 is achieved for the Nch of 5×1018 cm-3. The Dit of 1×1012 cm-2eV-1 and the EOT of 10 nm are responsible for the SS, confirmed by numerical simulation of GAA FETs. The drain current at VGS - VT = -2V and VDS = -1 V can reach 290 μA/μm for the device with the Nch of 8×1019 cm-3 and the Wfin of 9 nm, ~1.4X enhancement of the Ion as compared to Nch = 5×1018 cm-3. Note that the Ion of JL GAA nFETs with the Nch of 1×1019 is compatible with the JL GAA pFETs. As compared to INV Ge GAA pFETs, the device with 27-nm Wfinexhibits 49% mobility improvement at high overdrive voltage. The roll-off of mobility of the INV devices with the increasing inversion carrier density is mainly due to the surface roughness scattering (SRS) [3]. As a result, the JL GAA devices have the better immunity of SRS as compared to the INV devices.
Conclusion
With the removal of defective Ge near Ge/ Si interface, a defect-free Ge GAAFETs can be integrated on the Si platform. With the (111) sidewall-enhanced mobility, INV Ge GAA nFET is demonstrated to have ~2x enhanced Ion. The JL Ge GAA pFETs are also demonstrated with the SS of 95 mV/dec for the device with Nch of 5×1018 cm-3 and Ion of 290 μA/μm for the device with Nch of 8×1019 cm-3. Our results show that Ge GAAFETs is a promising candidate for future CMOS applications.
Reference
[1] C. Auth et al., 2012 Symp. on VLSI Tech., (2012) p. 131.
[2] Shu-Han Hsu et al., 2011 International Electron Devices Meeting (IEDM), (2011) p. 825.
[3] H. -S. Lan et al., Appl. Phys. Lett., 99 112109 (2011).