Plasma Post-Oxidation for High Mobility Strained-Ge pFETs with Aggressively Scaled High-κ Dielectrics

Abstract

High mobility materials such as Ge and III-V are currently being investigated to improve CMOS performance with continued scaling [1-3]. For p-channel devices, the maximum transport enhancement to silicon is achieved by maximizing both strain and Ge content in SiGe; uniaxially strained-Ge (s-Ge) should provide the highest transport enhancement relative to Si [4]. In order to scale s-Ge to short-channel, a scaled gate dielectric must be developed as well. In this work, we use plasma post-oxidation (PPO) [5] in order to maintain the high mobility of biaxially s-Ge while aggressively scaling to one of the lowest capacitance equivalent thicknesses (CETs) reported [6].

    Annular s-Ge p-MOSFETs (Fig. 1) were fabricated on biaxially s-Ge to evaluate the impact of plasma post-oxidation and highly scaled high-κ on mobility. An initial gate stack of 5Å Al₂O₃/20 Å HfO₂ was deposited via ALD and ex-situ PPO was performed on select samples before TiN was deposited and patterned. Ion implantation of boron was used to dope the source and drain regions followed by RTA at 625°C for 10s to activate the dopants. The fabrication was followed by a standard metallization process and a forming gas anneal for 30min at 450°C.

   Plasma post-oxidation greatly improves the gate control of the channel (Fig. 2). PPO increases the I_max/I_min of the drain current to 10⁴ compared to <10² for a device without PPO. The subthreshold swing is drastically improved and the V_t of the device after PPO is shifted in negative direction.  These characteristics suggest that PPO greatly reduces the D_it through oxidation of the Ge interface.  Because GeO_x is formed in the process, the EOT is increased and the gate leakage is also lowered. The split C-V measurements show that the CET is ~1.1 nm for the PPO treated devices. Here, the CET is taken at V_G = -0.5V ~ V_t - 0.7 V. Fig. 3 shows the split-CV hole mobility vs. inversion charge density (N_inv) for a typical device with PPO process and CET~1.1nm.  The mobility of a sample with similar structure and ozone surface passivation (CET~1.4nm at V_GS-V_t=-0.7V or CET~1.3nm taken from C_max [7]) is also overlaid. It is well known that CET scaling is required for aggressively scaled devices to maintain the electrostatic integrity. The device with PPO offers ~1.27X capacitance benefit over the sample with ozone passivation, at an over-drive of 0.7V, while slight mobility degradation of ~14% is measured at the same over-drive. To compare at a given N_inv, inset of Fig. 3 shows the hole mobility vs. constant over-drive CET at N_inv=5×10¹² and 10¹³ cm^-2. The mobility drop is 20% and 7% at N_inv=5×10¹² and 10¹³ cm^-2, respectively. This data indicates that both high mobility and low CET are maintained for s-Ge. The results are competitive with those reported in [6]. These results suggest that PPO could be a suitable method for making aggressively scaled high-κ for nanoscale s-Ge devices.

Acknowledgements

The authors thank G. Riggott and staff of IBM T.J. Watson for helpful discussions.

References

[1]     A. Khakifirooz and D.A. Antoniadis, in IEDM Tech. Dig., 2006.

[2]     S. Bedell et al., ECS Trans., 19, 1 (2009).

[3]     J. A. del Alamo, Nature Materials, 10, 11 (2011).

[4]     W. Chern, P. Hashemi, J. T. Teherani, T. Yu, D. A. Antoniadis, and J.L. Hoyt, IEEE Electron Dev. Lett., 35, 3 (2014).

[5]     R. Zhang, T. Iwasaki, N. Taoka, M. Takenaka, S. Takagi, Appl. Phys. Lett., 98, 11 (2011)

[6]     R. Zhang, W. Chern, X. Yu, M. Takenaka, J.L. Hoyt, S. Takagi, in IEDM Tech. Dig., 2013.

[7]     P. Hashemi et al., IEEE EDL, 33, 7 (2012).