(Invited) Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations

Tuesday, 7 October 2014: 14:10
Expo Center, 1st Floor, Universal 8 (Moon Palace Resort)
D. Lu (IBM), P. Morin (STMicroelectronics), B. Sahu (GLOBALFOUNDRIES), T. B. Hook, P. Hashemi, A. Scholze (IBM), B. Kim (Samsung Electronics), P. Kerber, A. Khakifirooz, P. Oldiges, K. Rim, and B. Doris (IBM)
We introduce SiGe MOSFET process integration and device impact from a simulation perspective.  Germanium is know to have a higher channel hole mobility.  Enhancement of hole velocity due to lattice mismatch strain in shilicon germanium epitaxial layers is significant.  Processing challenges include the elimination of interface trap states at the dielectric interface, fast diffusion of n-type dopants, defects in stress relaxed buffer and critical thickness limitations.  Uniaxial stress is beneficial for device performance. Transformation of biaxial stress to uniaxial is natural when etching silicon germanium into stripes.  From a device perspective, silicon germanium is useful for shifting MOSFET device Vth.