(Invited) Wafer-Level Integration of Embedded Cooling Approaches

Three dimensional integration of ICs allows the construction of dense electronic systems with increased communication bandwidth, due to reduced interconnect length between functional blocks, resulting in improved power efficiency. However, a higher density of components drives the package-level power density, requiring new thermal management solutions to keep components within thermal limits. Hence, we will present our thermal management roadmap for 3D stacks starting from single-side thermal management, to dual-side cold plates and finally to volumetric interlayer heat removal. We will also cover design aspects, achievable thermal performances and multiple challenges due to the integration of fluid structures into a microprocessor module.

Currently chip-level heat removal on the back-side of the microprocessor die has been demonstrated with sensible heat (single-phase) and latent heat (two-phase) cooling approaches. Water is the preferred fluid for single-phase cooling due to the high heat capacity of 4181 J/(kgK), supporting heat loads up to 700 W/cm² at a junction to fluid thermal gradient of 20K and a system pressure drop of 1 to 2 bars. The fluid is circulated through 300µm deep channels, enhancing the solid to fluid contact area. The low temperature gradient allows the extraction of hot water at 60°C, thus enabling the recovery of the dissipated heat into domestic heating networks. In contrast, refrigerants are used to take advantage of the latent heat of the cooling medium. Their main advantage is the high heat transfer coefficient at low flow rates, resulting in a low system pressure drop and hence low pumping power. However, the absolute system pressure can be up to 7 bar, resulting in higher mechanical requirements for the package.

Improved heat extraction can be achieved by dual-side cooling, which is implemented using an actively cooled Silicon interposer with electrical feed-through, realized by Through-Silicon-Vias (TSVs).  The chip is mounted on the interposer and a cold plate is attached on the back-side as done in the single-side cooling case. For water as the coolant, sealing features need to prevent shorting between TSVs. Hence, the implementation of simultaneous solder ring and pad structures is proposed (Figure 1.1). Considerations need to be taken regarding the design of the sealing ring in order to prevent local solder accumulation (“balling”, Figure 1.2) potentially resulting in electrical shorts. Sealing rings can be omitted when using dielectric refrigerants as in two-phase cooling. However, the limited TSV height results in microchannels with a moderate depth of 100µm and therefore, results in a low flow rate even at a large pressure drop. The consequence is a large temperature gradient between fluid inlet and outlet, due to coolant temperature increase or saturation temperature drop for single- or two-phase cooling. 

Finally, volumetric heat removal can be achieved by interlayer cooling which performance scales with the number of dies integrated in the chip stack. Within the chip stack, 50µm TSV pitches are required, compared to 200µm in the interposer, hence, constraining the coolant mass transport even more. Sophisticated fluid networks, such as 4-port fluid delivery, fluid focusing and varying pin densities are required to still obtain sufficient heat removal.

All three heat removal concepts can leverage wafer-level bonding as a cost efficient implementation in high-volume manufacturing. For single-side cooling, only thermal and mechanical requirements need to be fulfilled allowing for glass frit or silicon fusing bonding. Dual-side and interlayer cooling interfaces need to fullfil additional electrical requirements. Hence, techniques such as Cu-Cu thermo-compression or thin-film solder bonding using AuSn or CuSn were evaluated. Material compatibility with the cooling medium as well as system reliability are key aspects that need to be addressed. Finally, each of the proposed cooling solutions need to be coupled to a copper fluid loop. Such fluid connections from the low CTE and brittle Silicon to the high CTE and ductile copper is a challenge. We will present a solution using a elastomeric membrane and a highly filler polymer manifold to mitigate thermo-mechanical stress and the risk of failure.