Strained p-Channel MOSFET Fabrication Challenge and Perspective for the 28-Nm Technology Node and Beyond

Carrier mobility enhancement technique was introduced to ULSI manufacture since 90-nm technology node. As one of promising mobility enhancement techniques, the strain/stress at the channel region of metal-oxide-semiconductor field effect transistors (MOSFETs) modulates the lattice constant and band structure of silicon then enhances the hole/electron mobility. [1] The high mobility gives high source injection velocity into the quasi-ballistic transport channel which can provide high drive current and high circuit speed of MOSFETs. [2] Among a great variety of mobility enhancement techniques by applying stress to induce appropriate strain in the p-channel region, forming embedded epitaxial Si_1-xGe_x with recessed Source/Drain (S/D) structure has been reported as one powerful technique. [3] The Sigma-shaped silicon recess profile is applied before epitaxial Si_1-xGe_xgrowth, because the strain force on the channel of MOSFET is increased effectively by narrowing spacing between source and drain. [4]

In this manuscript, we utilized one-step and two-step dry etch process with the same alkaline solution wet etch to form Sigma-shaped silicon recess profile for the planar p-channel MOSFETs. After comparing the recess depth loading correlated to the pitch of gate electrodes (Table 1), we also studied the tunable capability and limitations on tip depth, tip proximity and total depth of Sigma-shaped trench for these two different dry etch processes. The strict profile control of Sigma-shaped profile is not only led by the device performance variation demand but also needed to get the excellent epitaxial Si_1-xGe_x crystallinity. Besides that, Si-C bond on the trench surface could inhibit the epitaxial Si_1-xGe_x growth, thus resulting in defects on S/D area. We proved that high H₂ volume ash process could effectively remove the Si-C bond at trench surface and greatly reduce the Si_1-xGe_xdefect counts. (Fig. 1)

Recently, the further down-scaling of planar MOSFETs technology is facing a serious physical limitation which results in short-channel effects (SCEs). Multiple-gate FETs or Fin structure FETs are already adopted in the fabrication process for the excellent control of SCEs from 20-nm technology node. Unlike the conventional planar transistor, a significant portion of the drain current is conducted along the fin sidewalls in FinFETs. Therefore, to realize a large mobility enhancement, the strain/stress techniques of FinFETs should be significantly different from embedded Si_1-xGe_x techniques of traditional planar devices. The Pi-shaped Si_1-xGe_x (Π-Si_1-xGe_x) should be induced to encapsulate the silicon on the top and sidewalls of the narrow fins. [5]

In this work, the Π-Si_1-xGe_x stressors should be grown on the top and sidewalls of fins in the S/D regions of p-channel FinFETs. However, due to the loading effect of traditional silicon nitride (SIN) spacer etch, the epitaxial Si_1-xGe_x growth could be hindered by the existence of SIN spacer stringer at the sides of the fin in some special pattern density area. To solve this issue, multi-cycle SIN etch process was attempted in the spacer open step. Compared with the conventional etch process, the multi-cycle SIN etch process delivers the excellent control of spacer pull back loading at universal pattern density area. (Fig. 2) In order to protect the SIN capping layer on the gate top corner and clearly remove the SIN spacer at the top area of fins, the gas types, gas ratio and other parameters are carefully optimized in SIN spacer etch process. We successfully decoupled the trade-off line of capping layer protection and the SIN spacer pull back. Additionally, by balancing the isotropic and anisotropic recess parts in the whole process, we demonstrated the recessed fin structure with flat and smooth surface on the top area, which would be benefit for future good crystalline and well controlled Π-Si_1-xGe_xgrowth. (Fig. 3)

ACKNOWLEDGMENT

This work was partially sponsored by Program of Shanghai Technology Chief Scientist (B type). 

References:

[1]. Hoyt. J. L., et al. Strained silicon MOSFET technology. In: IEDM Tech Dig;.P.23, (2002).

[2]. Liu, C. W., et al, IEEE CIRCUITS & DEVICES MAGAZINE,P21, (2005)

[3]. N. Tamura, et al, Junction Technology, P73, (2008)

[4]. H. Ohta, et al, Electron Devices Meeting,P 240, (2005)

[5]. Tan, K. M., et al, IEEE Electron. Device Lett., vol. 28, issue 10, P905 (2007)