Strained p-Channel MOSFET Fabrication Challenge and Perspective for the 28-Nm Technology Node and Beyond
In this manuscript, we utilized one-step and two-step dry etch process with the same alkaline solution wet etch to form Sigma-shaped silicon recess profile for the planar p-channel MOSFETs. After comparing the recess depth loading correlated to the pitch of gate electrodes (Table 1), we also studied the tunable capability and limitations on tip depth, tip proximity and total depth of Sigma-shaped trench for these two different dry etch processes. The strict profile control of Sigma-shaped profile is not only led by the device performance variation demand but also needed to get the excellent epitaxial Si1-xGex crystallinity. Besides that, Si-C bond on the trench surface could inhibit the epitaxial Si1-xGex growth, thus resulting in defects on S/D area. We proved that high H2 volume ash process could effectively remove the Si-C bond at trench surface and greatly reduce the Si1-xGexdefect counts. (Fig. 1)
Recently, the further down-scaling of planar MOSFETs technology is facing a serious physical limitation which results in short-channel effects (SCEs). Multiple-gate FETs or Fin structure FETs are already adopted in the fabrication process for the excellent control of SCEs from 20-nm technology node. Unlike the conventional planar transistor, a significant portion of the drain current is conducted along the fin sidewalls in FinFETs. Therefore, to realize a large mobility enhancement, the strain/stress techniques of FinFETs should be significantly different from embedded Si1-xGex techniques of traditional planar devices. The Pi-shaped Si1-xGex (Π-Si1-xGex) should be induced to encapsulate the silicon on the top and sidewalls of the narrow fins. 
In this work, the Π-Si1-xGex stressors should be grown on the top and sidewalls of fins in the S/D regions of p-channel FinFETs. However, due to the loading effect of traditional silicon nitride (SIN) spacer etch, the epitaxial Si1-xGex growth could be hindered by the existence of SIN spacer stringer at the sides of the fin in some special pattern density area. To solve this issue, multi-cycle SIN etch process was attempted in the spacer open step. Compared with the conventional etch process, the multi-cycle SIN etch process delivers the excellent control of spacer pull back loading at universal pattern density area. (Fig. 2) In order to protect the SIN capping layer on the gate top corner and clearly remove the SIN spacer at the top area of fins, the gas types, gas ratio and other parameters are carefully optimized in SIN spacer etch process. We successfully decoupled the trade-off line of capping layer protection and the SIN spacer pull back. Additionally, by balancing the isotropic and anisotropic recess parts in the whole process, we demonstrated the recessed fin structure with flat and smooth surface on the top area, which would be benefit for future good crystalline and well controlled Π-Si1-xGexgrowth. (Fig. 3)
This work was partially sponsored by Program of Shanghai Technology Chief Scientist (B type).
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