Process Optimization on Self-Aligned Double Patterned Fin Formation

As the feature size of integrated circuit (IC) keeps shrinking, self-aligned double patterning (SADP) has been widely used in 14nm technology node and beyond.[1] In SADP Fin etch,the precise pattern transfer is critical for the robust device performance. However, compared with single patterning scheme, SADP poses more challenges from the point of view of even/odd issue, RIE-lag loading and line width roughness (LWR) control.In this work,we delivered the overall solution by introducing the bias pulsing plasma etch and mixed mode pulsing(MMP) concept in mandrel and shallow trench isolation (STI) to address the rigorous loading control [2] between dense and isolated patterns, the synchronous pulsing scheme to form the spacer with almost flat spacer top, thus benefiting the even/odd performance in SADP fin etch. Besides,we also investigated the effects of plasma ribbon beam[3], chemical down-stream etch (CDE) and high conductance on LWR improvement, respectively.

Rigorous loading control at dense and isolated patterns is important to ensure the robust device performance.This is especially true at sub20nm technology node. In SADP Fin etch, the dense-isolated loading (including CD, depth and sidewall angle) mainly comes from mandrel etch and STI etch process. As is well known, etch by-product deposition mode behaves quite differently between dense and isolated area. In traditional continuous wave (CW) plasma, it’s quite hard to tackle such notorious loading for its inherent high Te induced ionization. While, the bias pulsing plasma paves the way to alleviate such toggled loading for less bombardment during the bias-off period could reduce the etch by-product formation to some extent.Moreover, MMP plasma enables precise etch process control by repeatedly resetting each phase to initial state which could eliminate most of process induced loading accumulation.Based on the above learning, we induced MMP concept in STI etch process and successfully developed a well-controlled loading performance on Fin (shown in Fig1).

In SADP Fin etch,both spacer top profile and mandrel performance are extremely critical to final even/odd performance. On one hand, the mandrel performance could result in the difference of depth and line edge roughness (LER) between mandrel space and spacer space as schematically shown in Fig 2a. Such even/odd distribution could finally introduce the huge variation of the effective Fin height. Among three different mandrel materials, we found such even/odd issue could be improved by means of mandrel material selection.On the other hand, traditional spacer etch process usually delivers the undesired spacer shoulder loss(schematically shown in Fig2a).Such asymmetric spacer height pattern could be directly transferred to Fin formation and easily induce the asymmetric stress distribution on Fin, which could potentially lead to Fin distortion. Here, we resorted to the synchronous pulsing scheme to reshape the spacer top profile without the excessive loss of spacer height.

LWR has aroused much attention as CMOS is being scaled down to FinFET. Both high frequency LWR and low frequency LWR have to be addressed at mandrel definition as the LWR of ALD spacer strongly depend on mandrel LWR. We leveraged plasma ribbon beam to improve low-frequency LWR of photo resist and did achieve the remarkable improvement. However, the substrate damage and photo resist loss need special method such as synchronous pulsing scheme to reduce photo resist loss during etch process. Besides, CDE was used to improve high-frequency LWR at mandrel and Fin. However, the result is quite different between them. 30% LWR reduction could be seen on Fin while it does NOT work on mandrel at all. This might come from the material difference or insufficient CD loss. Last but not least, mandrel etch itself could deliver better high LWR performance with high conductance and special photo resist treatment.

ACKNOWLEDGMENT

This work was partially sponsored by Program of Shanghai Technology Chief Scientist (B type). 

References:

[1] M.-S. Kim, et al, UTIS, “Self-Aligned Double Patterning of Ix nm FinFET;ANew Device Integration through the Challenging Geometries”, 2013
[2] Y. Wang, et al, CSTIC, “Process Loading Reduction on SADP FinFET Etch”, 2015
[3] X. Meng, et al, CSTIC, “The Improvement of Poly-Si Gate Line Width Roughness”, 2014