(Invited) Material and Device Integration for Hybrid III-V/SiGe CMOS Technology

Tuesday, October 13, 2015: 11:30
103-B (Phoenix Convention Center)


Continuous scaling of CMOS technology has revolutionized our society. Although the microelectronic industry has benefited economically from the constant scaling of MOSFET dimensions, serious technical challenges have now emerged that could become show-stoppers. Pure lithographic scaling is no longer sufficient to bring about expected benefits as both performance and power consumption metrics degrade owing to short channel effects. As the overall industry is shifting towards ‘mobile and connected devices’, the need for reducing power consumption is becoming a very critical requirement for sub-14 nm nodes. Besides this, the demand for integrating multiple functionalities on chip (Systems-on-Chip) is also growing. In the past decade, considerable efforts have been made for innovation-driven scaling by introduction of novel materials (high-k/metal gate) and new device architectures (strained silicon, FDSOI, FinFETs etc.). These have helped us reap performance benefits of reduced MOSFET dimensions. As we go to sub-14 nm nodes, limitations in lithography and silicon material properties are becoming more serious than ever. In order to continue scaling, innovations in channel materials and integration is required. High-mobility channel materials such as Ge, SiGe and III-V compound semiconductors are envisaged to provide necessary power-performance benefits in these nodes. In order to provide a robust, manufacturable CMOS technology these will need to be co-integrated on the same platform. Various challenges have to be tackled for achieving high-mobility CMOS technology. These range from material integration aspect to device fabrication. In this paper we will first detail various methods of integrating the III-V materials which could provide a scalable and manufacturable platform. Based on these, we will then review the various III-V device architecture and processing methods (high-k/III-V interface, source/drain contacts, III-V MOSFETs) that can enable high performance MOSFETs. We will further discuss challenges and strategies to develop a scaled hybrid III-V/SiGe CMOS platform in various architectures (2D vs 3D monolithic) and demonstrate hybrid circuit results.