Ge and III-V Technologies 2

Tuesday, October 13, 2015: 10:00-12:00
103-B (Phoenix Convention Center)
Chairs:
Hiroshi Iwai and Osamu Nakatsuka
10:00
1084
(Invited) Tunneling FET Technologies Using III-V and Ge Materials
S. Takagi (The University of Tokyo, JST-CREST), M. Kim, M. Noguchi (The University of Tokyo), K. Nishi (The University of Tokyo, JST-CREST), and M. Takenaka (The University of Tokyo, JST-CREST)
10:30
1085
(Invited) Surrounding-Gate Tunnel FET Using InAs/Si Heterojunction
K. Tomioka (GS-IST, RCIQE, Hokkaido University, Japan Science and Technology Agency (JST) - PRESTO), J. Motohisa (Hokkaido University), and T. Fukui (Hokkaido Unversity)
11:00
1086
(Invited) On the Electrical Activity of Extended Defects in High-Mobility Channel Materials
E. Simoen, G. Eneman (Imec), A. Y. Hikavyy (imec), R. Loo (imec, Belgium), S. Gupta, C. Merckling (imec), A. Alian (Imec), A. Schulze, M. Caymax (imec, Belgium), R. Langer, K. Barla (IMEC), and C. Claeys (Imec)
 
1087
(Invited) Material and Device Integration for Hybrid III-V/SiGe CMOS Technology (Cancelled)
See more of: G04: ULSI Process Integration 9
See more of: Electronic Materials and Processing
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