(Invited) Tunneling FET Technologies Using III-V and Ge Materials

Tuesday, October 13, 2015: 10:00
103-B (Phoenix Convention Center)
S. Takagi (The University of Tokyo, JST-CREST), M. Kim, M. Noguchi (The University of Tokyo), K. Nishi (The University of Tokyo, JST-CREST), and M. Takenaka (The University of Tokyo, JST-CREST)

Since TFETs based on band-to-band tunneling are expected as ultra-low power devices, development of the optimum materials, structures and fabrication process have been strongly pursued for realizing both low SS of sub-60 mV/dec. and high drain Ion/Ioff ratio at the same time. For this purpose, the reduction in the effective band gap is important for enhancing tunneling current. Thus, we are currently focusing planar-type TFETs using Ge/III-V and their hetero-structures. One of the key issues for TFETs is the formation of the steep and high quality source junctions, which provide both high tunneling current and low off current. In this talk, we address two types of planar TFETs utilizing the Ge/strained Si (sSi) hetero-structure and the InGaAs channels where in-situ doping p+ Ge/sSi and Zn-diffused p+ InGaAs source junctions are employed for realizing steep and defect-less tunneling junction formation.

As for the TFET channels, sSi is a realistic material, because of the smaller bandgap. For the TFET sources, pure Ge sources grown on Si are expected to provide higher tunneling current [1, 2], because of the type-II staggered band alignment between Ge and Si [3]. Thus, we have combined the Ge source with strained-SOI channels [4, 5]. The higher Ev edge of the Ge-source and the lower Ec edge of tensile-strained Si result in reduction in the effective band gap, leading to the increase the tunneling probability with maintaining the relatively large Eg of sSi in the drain regions, which can suppress the ambipolar leakage current. It is found that an increase in strain leads to the increase in Ion and the decrease in IG, resulting in high Ion/Ioff ratio because of higher tunneling probability and higher barrier height between insulators and sSi [6]. It is found that PMA temperature strongly affects the electrical properties. The Ion/Ioff ratio is maximized after 400 oC PMA, which amounts to 4.4E7, 2.2E7 and 3.7E7 for the unstrained, 0.8 and 1.1 % strained SOI TFETs, respectively. Also, higher PMA temperature also significantly reduces SS. The unstrained, 0.8 and 1.1 % strained SOI TFETs after 400 oC PMA yield SSmin of 55, 49 and 29 mV/dec, respectively, at room temperature. This better performance with higher PMA temperature is attributed to lower Dit at the Si MOS interfaces [7]. Also, the ID-VG characteristics are almost independent of temperature, meaning that any defect-related currents are effectively suppressed and the tunneling current dominates over the operation of the devices.

InGaAs is a promising material of TFETs, because of the high tunneling probability due to the narrow and direct bandgap. Here, formation of the source junctions with defect-free and steep impurity profiles is mandatory for InGaAs TFETs. From this viewpoint, we have introduced solid- phase Zn diffusion in InGaAs through utilizing the inherent diffusion property of Zn in InGaAs creating defect-less extremely-steep profiles [8]. It is found from SIMS that the steepness of the Zn profiles is less than 3.5 nm/dec. This result is consistent with the model that diffusion constant of Zn in InGaAs is proportional to the square of the Zn concentration [9], ensuring the automatic realization of the steep impurity profile. The devices exhibited the small SSmin of 64 mV/dec. and the large Ion/Ioff ratio over 1E6 at the same time as the planar-type III-V TFETs with EOT of 1.3 nm. We have also found almost no temperature dependence of ID, confirming the dominance of band-to-band tunneling on the present devices. These results show the superior p+/n junctions formed by Zn solid phase diffusion in InGaAs.

In conclusion, the enhancement of tunneling probability by utilizing III-V/Ge materials is quite effective in improving the performance of TFETs. Superior source junction formation and MOS interface control technologies are key factors to realize TFETs using III-V/Ge.

This work was partially supported by JST-CREST, and JSPS Core-to-Core Program, A. Advanced Research Networks. We would be grateful to Drs. H. Yamada, O. Ichikawa, T. Osada and M. Hata in Sumitomo Chemical Corporation for continuous support on III-V epi substrates and SOITECH for providing strained SOI substrates.

References  [1] S. H. Kim et al., VLSI Symp. (2009) 178 [2] G. Han et al., APL 98 (2011) 153502 [3] O. M. Nayfeh et al., EDL 29 (2008) 1074 [4] M.-S. Kim et al, Thin Solid Films, 557 (2012) 298 [5] M.-S. Kim et al., IEDM (2014) 331 [6] T. Hoshii et al., JJAP 46 (2007) 2122 [7] M.-S. Kim et al., TED 62 (2015) 9 [8] M. Noguchi et al., IEDM (2013) 683 [9] Y. Yamamoto et al., JJAP 19 (1980) 121