(Invited) Surrounding-Gate Tunnel FET Using InAs/Si Heterojunction

Tuesday, October 13, 2015: 10:30
103-B (Phoenix Convention Center)
K. Tomioka (GS-IST, RCIQE, Hokkaido University, Japan Science and Technology Agency (JST) - PRESTO), J. Motohisa (Hokkaido University), and T. Fukui (Hokkaido Unversity)
A main goal of future electronic circuits is lower huge power consumption of LSIs while enhancing the chip performance.  The Si-CMOS technologies are expected to change their gate-architecture, channel material, and transport mechanism to overcome the apparently-paradoxical demands which is owing to the inherent issues in miniaturization of Si MOSFETs. Enhanced short-channel effect and leakage current is emerged problem in further scaling of the transistor size. To avoid these issues, the gate structure have already changed into fin architecture [1] and will shifted to gate-all-around (GAA) [2] or surrounding-gate structure [3].

As for channel materials, III-V and Ge are promising alternative channels [4,5] because of higher carrier mobility and low electron/hole effective mass achieving higher ON-state current under lower bias. Since these materials tend to exhibit slightly high leakage current due to tunneling leakage, multi-gate architecture for these channel would necessary for decreasing leakage current. Furthermore, the inherent mobility mismatch between the III-V and Ge will be bottleneck in device-integration scheme to match current density. In near future, the III-V channel has no other choice except for vertical channel architecture to avoid the issue. In this regard, a co-integration technique of vertical III-V channel with p-channel Ge will be required for Si-CMOS.

Final target is beating physical limit of conventional MOSFET especially subthreshold slope (SS) due to carrier thermal diffusion (SS = 2.3 kBT/q = 60 mV/dec). This limitation will stop further scaling of the power consumption even if a multi-gate architecture and III-V/Ge channel are applied. The steep-slope transistors such as tunnel FETs (TFETs) and impact ionization FETs [6] have therefore been proposed to overcome the limitation and to reduce supply voltage to sub-0.5 V in future LSI. These distinct features should be mutually addressed as extended CMOS technologies. In this regard, the selective-area epitaxy of III-Vs on Si will play an important role as integration technique of vertical III-V channels on Si and Ge, and the excellent III-V/Si heterojunction can assist to connect these challenges smoothly. In this paper, we review recent advances in direct integration of vertical III-V nanowire (NW)-channel on Si and FET application such as vertical III-V NW surrounding-gate transistors (SGTs) and tunneling FET (TFETs) using III-V NW/Si heterojunctions.

In addition to the high-performance vertical FET application using the III-V nanowire-channel on Si, the III-V/Si heterojunction, which is formed underneath the small footprint of the III-V nanowire, is a promising junction for the use of steep-SS switches because this heterojunction shows preudo-staggered Type-II band discontinuity in the case of the n-III-V nanowire/p+-Si heterojunctions. Under the reverse bias condition, a large Zener current depending on the carrier concentration of p-Si occurs, indicating that this current is modulated by the gate bias. Once the Fermi level is laid in the valence band in p-Si with a high carrier concentration, band-to-band tunneling appears under the forward bias.

In case of a vertical steep-SS switch using the III-V nanowire/Si heterojunction, controlling the series resistance is important to achieve a steeper SS (< 60 mV/dec) because the SS is the function of VG and VDS [7]. This means a large electrical field should be induced at the heterojunction or channel region under a lower VG and VDS. In this regard, reducing the diameter of the heterojunction to avoid the trap-assisted tunneling process via defect level and forming an intrinsic layer are important for obtaining steep SS property. The device using an InAs nanowire (30 nm in diameter)/Si heterojunction demonstrated a steep SS (minimum SS = 12 mV/dec) at room temperature [7, 8].

[1].      I. Ferain et al., Nature 479 (2011) 310.

[2].      J. J. Gu et al., IEEE IEDM Tech. Dig. 769 (2011).

[3].      H. Takato et al., IEEE TED 38 (1991) 573.

[4].      J. A. del Alamo, Nature 479 (2011) 317.

[5].      H. Riel et al., MRS Bulletin 39 (2014) 668.

[6].      A. M. Ionescu et al., Nature 479 (2011) 329.     

[7].      K. Tomioka et al., VLSI Symp. Tech. Dig. (2012)  47

[8].      K. Tomioka et al., Nano Lett. 13 (2013) 5822.