(Invited) On the Electrical Activity of Extended Defects in High-Mobility Channel Materials

^aalso at E.E. Dept. KU Leuven, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium

     Since the 45 nm CMOS node, high-k gate dielectrics and strain engineering go hand in hand to further boost the transistor performance. An example of a so-called global strain platform relies on a thin strained-silicon (sSi) layer on top of a strain-relaxed Si_1-xGe_x buffer (SRB) (Fig. 1). In addition, replacing thermally grown SiO₂ by a deposited dielectric opens the door for the implementation of so-called high-mobility channel materials (Ge – pMOS; In_xGa_1-xAs – nMOS;...), which can be grown hetero-epitaxially on a silicon substrate. Due to the lattice mismatch of most of these materials with silicon, strain relaxation will occur above a certain critical thickness, leading to the introduction of both misfit and threading dislocations (TDs). It is well-known that dislocations introduce a one-dimensional band of states in the band-gap and hence are electrically active [1],[2]. The aim of the present review is to address the impact of such extended defects on the electrical performance of simple devices (p-n junctions, MOSFETs,...) for various high-mobility materials.

    A first example which will be discussed is the impact of TDs on the current-voltage (I-V) characteristics of p-n junctions fabricated in sSi and relaxed-Ge-on-Si substrates. As can be derived from Fig. 1, the depletion region mainly extends in the SiGe SRB, so that the electrical activity of the dislocations in this layer will be probed. It is clear from Fig. 2 that the reverse current I_R of the diodes more or less proportionally increases with the density of TDs [3]. The same applies for the recombination and generation lifetime. Similar studies have been carried out for p-n junctions fabricated in a Si_0.2Ge_0.8 SRB and in relaxed Ge-on-Si epi layers. Summarizing all these results in Fig. 3, one can observe that the area leakage current density increases proportionally with the density of TDs and exponentially with the Ge content [4]. The latter can be explained by considering the impact on the band gap, yielding an exponential increase of the intrinsic carrier density. Comparing with Fig. 3b, it is clear that there exists a trade-off between leakage current density and epi layer thickness: thinner relaxed Ge layers on silicon will have a higher equilibrium TD density [5] and, hence, leakage current. However, considering a typical SRAM cell design, it can be concluded that for typical TDD values of 10⁷-10⁸ cm^-2, the contribution to the off-state leakage is negligible compared with the contribution of the perimeter.

     A second example investigates the impact of anti-phase boundaries (APBs) on the reverse current of p-n junctions fabricated in GaAs (Fig. 4a) will be discussed. As can be derived from Fig. 4b, there is a modest increase of I_Rbetween on-axis junctions with a high APB density and off-axis diodes. Overall, it has been concluded that APBs are not so efficient leakage generators in GaAs.

Finally, the impact of TDs on other device parameters, like the mobility or the threshold voltage of a MOSFET will be discussed.

References

[1] W. Schröter and H. Cerva, Solid State Phenomen., 85-86, p. 67 (2002).

[2] E. Simoen et al., J. Electrochem. Soc., 158, p. R27 (2011).

[3] G. Eneman et al., Appl. Phys. Lett., 87, p. 192112 (2005).

[4] E. Simoen et al., J. Electrochem. Soc., 157, p. R1 (2010).

[5] G. Wang et al., Appl. Phys. Lett., 94, p. 102115-1 (2009).