(Invited) Si Photonics and Recent Challenges for on-Chip WDM

A trend of high speed computing and communication has demonstrated incredible performance increase, 1000x in every 10yrs. Such enhancements have been realized partly due to Moore’s law based and parallelism based progresses [1]. To keep up such a trend for future, we have to integrate photonics on a chip, i.e., Si photonics, especially on-chip WDM (wavelength division multiplexing) architecture [2]. In the history of the fiber optics, WDM has brought significant increase in bandwidth of optical communication and currently the channel spacing in WDM is as small as 0.8 nm and will soon be 0.4 nm. However, Si photonics has used coarse WDM where the channel spacing is as large as 10nm. The reason for the large spacing is a large TO (thermooptics) coefficient of Si. Due to chip temperature fluctuation on a chip, wavelength is changed widely, malfunctioning WDM. This is the fundamental limit in shrinking the wavelength spacing. In other words, the key challenge to implement on-chip WDM is to lock its channel wavelength within a given channel spacing. In this talk we will focus on silicon nitride based Si photonics, i.e., medium index contrast optics, MiDex Si photonics to lock the channel wavelength within the current dense WDM (DWDM) in optical fiber communication, i.e., 0.8nm spacing [3].

Fig. 1 shows bending radii of various waveguides vs. index difference between the core and cladding of the waveguide. Generally, Si waveguide and SiO2 cladding have been used in Si photonics, where index difference is 2.0. The materials set has a high index contrast, i.e., here we will refer it to as HiDex (high index contrast). The advantage is a sharp bending of the waveguide, which reduces device footfprints and allows high density integration of optical devices on a chip. Althougt the disadvantage is large light propagation loss, Si process technology allows to minimize the roughness of waveguide to reduce the loss to ~1dB/cm. It is known however that Si has a large TO coefficient, i.e., temperature dependence of refractive index. It has been reported that chip temperature has changed about 50˚C during its operation. Thus, on-chip temperature fluctuation changes wavelength, malfunctioning of WDM. To avoid it, a large channel spacing, i.e., 10nm has been chosen.

We have been focusing a slightly smaller index contrast system in the following two reasons: When we choose SiNx waveguide and SiO2 cladding, the minimum bending radius is 10 µm which is still small enough and the TO coefficient of SiNx is ~1/10 of that of Si. This indicates this materials system should be robust against temperature fluctuation on a chip. Of course Planar Lightwave Circuit based on silica fiber technology has smaller TO coefficient, here we refer it to as LoDex (low index contrast), but the bending radii should be ~1cm. Thus, we have proposed MiDex Si photonics instead of current HiDex Si photonics.

SiNx (0.6-0.8 µm thick) can be deposited on SiO2 (2µm thick) using a physical vapor deposition (PVD) technique. Chemical vapor deposition techniques have widely been used, but CVD SiNx contains N-H bonds that absorb 1520nm, that is in optical communication wavelength range of 1550nm. To dissociate H from SiNx, CVD SiNx should be annealed at high temperature such as 1100˚C. To avoid such high temperature annealing, we have chosen PVD SiNx, which should be free from N-H bonds. We have demonstrated SiNx without such absorption. The present report has verified the advantage of PVD SiNx over CVD SiNx, temperature stability of filter characteristics of ring based resonators, and athermalization using polymer materials. 

References

[1] http://www.top500.org.

[2] K. Wada, et al. The Proceedings of IEEE, 97, 1329, 2009.

[3] L.C. Kimerling, et al., MRS Bulletin, 39, 687, 2014.